<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/63848>63848</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Consider reducing 64-bit shifts with clamped shift amounts to 32-bit
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AMDGPU,
            missed-optimization
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            bcahoon
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          arsenm
      </td>
    </tr>
</table>

<pre>
    Currently the backend tries to reduce 64-bit shift by constant to 32-bit shifts when possible. This can be extended to cases with variable but known bounds. https://alive2.llvm.org/ce/z/_56Y57

```
declare i32 @llvm.smax.i32(i32, i32)
declare i32 @llvm.umax.i32(i32, i32)

; noundef is to stop alive timeouts
define i64 @src(i64 noundef %arg0, i32 noundef %arg1) {
  %min = call i32 @llvm.umax.i32(i32 %arg1, i32 32)
 %shift.amt = zext i32 %min to i64
  %shl = shl i64 %arg0, %shift.amt
 ret i64 %shl
}

define i64 @tgt(i64 %arg0, i32 %arg1) {
 %lo.bits = trunc i64 %arg0 to i32
  %sub = add i32 %arg1, -32
  %min = call i32 @llvm.smax.i32(i32 %sub, i32 0)
  %shl = shl i32 %lo.bits, %min
  %insert.1 = insertelement <2 x i32> <i32 0, i32 poison>, i32 %shl, i64 1
  %bitcast = bitcast <2 x i32> %insert.1 to i64
  ret i64 %bitcast
}

```

If I codegen these two options, on quarter rate 64-bit shift targets, I believe option 2 wins out in cycle count (for much larger code size)
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJx8lE1v4zYQhn8NfRlEkEayLB90SOJ1kUOBHtpDTwVFjS12KdLlUHGSX1-QVtay9wMwSFOaj3ce2q9k1kdL1Ir1k0DslBycswJRrHcrOYXB-VZ6JjuuOte_t8-T92SDeYcwEHRSfSXbQ_CaGIIDT_2kCOrqodMBeNCHAN07KGc5SBtiSInXdwzngSycHLPuDGXw56AZlLTQEdBbINtTH5OUZGI46zDAq_RadoagmwJ8te5soXOT7TmDIYQTi_JR4F7gXhr9SpgZ8zpmzh8F7hUJ3H8I3P-zrv9eb0S-E_njvNb5_EnHnpSRnkCXCKLKUw0e5VumSxTYpPUZ0rb9ecb0y4x5LZ_ARv10AJ0YcnAnSOIh6JHcFPizxUFbAl1XsQN7FevW1bd0gWvpj_nc5-5xIXALYvN0KQXx6agtiHIHShrzC93XApe6ixHiq3SRmRxDqvVBbwHmpFg_uKh30ZQHkwLjnia5il4WmzM8hc8oHsxMbLNbArylEo5hpnJH44cUBK6NyzodOGkKfrJqqSrJL3Epf-pSqOx7uGPzcBP4U7j8HVyeuk-V-RXtd7AuwbPemdeo7SJcWyYfsiLlXA5kaCQb7-YZ4S0NU36Jp7nbpe3JaXZWlF8WtCLveKorKBY9Oh2U5MtlX7_fFF8Iub3-xW3OqT-80bv_4mV9OcALKNfTkWz0HiYIZwfuFLSzCYez8N8kfSAPXoY7EwrSH-mC7QU6MppeaU4GhLO2DG4KoC2od2UIlJsiNWwOzsM4qQFMrOCTBGD9QQK3q74t-225lStqi7rZ4roocb0aWtpQU_RlVTdbKutKFR01m4OssFY5IhUr3WKOZb4pygKxqaoM842qSTWo1huqpRRVTqPU5pt9rTTzRG1dNlWzMrIjw5-efTFhUT4-_r777Y-_onnjs0AcNTP1D3HKUX_IOOts7L6NZR-66cjxZ6k58LVR0MFQ--ws6z6yjJau7fGG5-zFysjxRP3MWI4RGl9NfjV5096a8lGHYeoy5UaB-9hy3h5O3v1LKgjcp0FZ4D7N-n8AAAD___w1-Go">