<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/63747>63747</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            riscv: sfence.vma inline assembly is miscompiled
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          X547
      </td>
    </tr>
</table>

<pre>
    Clang: https://godbolt.org/z/afaMvnMrr
GCC: https://godbolt.org/z/nYEK9ozjP

Note that Clang use hardwired zero X0 register for both global and ASID 0 `sfence.vma` instruction, but GCC avoid using X0 when using ASID.

>From RISC-V privileged spec:
> If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page
tables, for all address spaces. The fence also invalidates all address-translation cache entries,
for all address spaces.
> 
> If rs1=x0 and rs2̸=x0, the fence orders all reads and writes made to any level of the page
tables, but only for the address space identified by integer register rs2. Accesses to global
mappings (see Section 4.3.1) are not ordered. The fence also invalidates all address-translation
cache entries matching the address space identified by integer register rs2, except for entries
containing global mappings.

> If the implementation does not provide ASIDs, or software chooses to always use ASID 0,
then after every satp write, software should execute SFENCE.VMA with rs1=x0. In the
common case that no global translations have been modified, **rs2 should be set to a register
other than x0 but which contains the value zero**, so that global translations are not flushed.
</pre>
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