<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/63596>63596</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] Incorrect f16 vector load + f32 extension folding
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            bug,
            backend:RISC-V
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          dcaballe
      </td>
    </tr>
</table>

<pre>
    Hi all,

It looks like the RISC-V backend is incorrectly trying to fold an f16 load + f32 ext into a widening load?

```
define <4 x float> @tensor_fp16_dispatch_0_generic_4_f16(ptr %0) {
  %2 = load <4 x half>, ptr %0, align 2
  %3 = fpext <4 x half> %2 to <4 x float>
  ret <4 x float> %3
}
```

```
llc -O2 -mattr=+m,+a,+f,+d,+v -mtriple=riscv64 -target-abi=lp64d -riscv-v-fixed-length-vector-lmul-max=8 f16load_ext.ll 
LLVM ERROR: Cannot select: t12: v4f32,ch = load<(load (s64) from %ir.0, align 2), anyext from v4f16> t0, t2, undef:i64
  t2: i64,ch = CopyFromReg t0, Register:i64 %0
    t1: i64 = Register %0
 t4: i64 = undef
```
</pre>
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