<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/63395>63395</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            build with AArch64 feature `ZeroCycleRegMove ` crashes
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          linzj
      </td>
    </tr>
</table>

<pre>
    POC:
```c
int foo(int a, int b, int c) {
  register int ret asm("w3");
  if (a == 0xa) {
    asm volatile("eor %w0, %w1, %w2\n": "=r"(ret) : "r"(b), "r"(c));
  } else {
    ret = 0;
  }
  return ret;
}
```

build command:
```sh
clang -target aarch64-linux-android -Xclang -target-feature -Xclang "+zcm"   -O3 -S /tmp/poc.c
```

ROOTCAUSE:
```c++
      if (Subtarget.hasZeroCycleRegMove()) {
        // Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move.
        MCRegister DestRegX = TRI->getMatchingSuperReg(
            DestReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
        MCRegister SrcRegX = TRI->getMatchingSuperReg(
 =>           SrcReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
```
When getting the source super register for wzr, the targeting register class is wrong. wzr and xzr are not inside GPR64spRegClass. So the SrcRegX is undefined `undef $noreg`:
```
  $x0 = ORRXrs $xzr, undef $noreg, 0, implicit $wzr, debug-location !26; /tmp/poc.c:8:3
```

Change the source to
```c++
 MCRegister SrcRegX = TRI->getMatchingSuperReg(
            SrcReg, AArch64::sub_32, &AArch64::GPR64RegClass);

```
The poc compiled.
And the machine code is correct:
```
  $x0 = ORRXrs $xzr, undef $xzr, 0, implicit $wzr, debug-location !26; /tmp/poc.c:8:3
```
</pre>
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