<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/63163>63163</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            test-suite case revertBit may overflow and return unexpected error
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Yunzezhu94
      </td>
    </tr>
</table>

<pre>
    When compiling test-suite case reverBit,  in following part:
  ```
for (int i = 0; i < NUM; ++i) {
    sum32 += ReverseBits32(i);
    sum64 += ReverseBits64(i);
  }
```
in certain situation adding up sum64 value generates overflow value and cause unexpected error on return.
For example:
when compiling with attributes: `clang -DNDEBUG  -latomic -march=rv32imafdcv -DSMALL_PROBLEM_SIZE -O3 -DNDEBUG   -w -Werror=date-time -Wno-implicit-int revertBits.c`
in ir it generates poison value:
```
13: ; preds = %1
  %14 = tail call i32 @llvm.vscale.i32()
  %15 = shl nuw nsw i32 %14, 1
  %16 = urem i32 16777216, %15
  %17 = sub nuw nsw i32 16777216, %16
  %18 = tail call <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
  %19 = tail call i32 @llvm.vscale.i32()
  %20 = shl nuw nsw i32 %19, 1
  %21 = insertelement <vscale x 2 x i32> poison, i32 %20, i64 0
  %22 = shufflevector <vscale x 2 x i32> %21, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
  %23 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %7, i64 0
  %24 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %10, i64 0
  %25 = tail call i32 @llvm.vscale.i32()
  %26 = shl nuw nsw i32 %25, 1
  br label %27
```
And return an non-zero final sum64 value, even if each `__builtin_bitreverse64` returns true result.
</pre>
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