<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/63155>63155</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [X86] Enabling AVX512 results in worse codegen on smaller registers.
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Sp00ph
      </td>
    </tr>
</table>

<pre>
    I tried this code:

```ll
define i8 @zero_bytes_bitmask(i64 %word) {
    %v = bitcast i64 %word to <8 x i8>
    %mask = icmp eq <8 x i8> %v, zeroinitializer
    %ret = bitcast <8 x i1> %mask to i8
    ret i8 %ret
}
```

Compiling this with just `clang -O3` generates this assembly:

```asm
zero_bytes_bitmask:                     # @zero_bytes_bitmask
        movq    xmm0, rdi
        pxor    xmm1, xmm1
        pcmpeqb xmm1, xmm0
        pmovmskb        eax, xmm1
 ret
```

Enabling AVX512 (`-mavx512f`) causes more instructions to be generated:

```asm
zero_bytes_bitmask:                     # @zero_bytes_bitmask
        vmovq   xmm0, rdi
        vpxor   xmm1, xmm1, xmm1
        vpcmpeqb        xmm0, xmm0, xmm1
        vpmovsxbd zmm0, xmm0
        vptestmd        k0, zmm0, zmm0
        kmovw eax, k0
        vzeroupper
        ret
```

I would've expected the code generator to prefer the baseline assembly even when AVX512 is enabled, as it results in less instructions overall.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJy8lMGO4jgQhp_GXEqNHIeYcMhhZhikOe1hpdXcRnZSBA92nHY5ge6nXzmQHqC797gRworz12_7K1cpItN2iBUrvrJiu1BDPPhQ_d1z3h8W2jcv1Q-IwWAD8WAIat8gy78wvmV8_pf88rP2MtHg3nQIpgS24q8Y_C_9EpF-aROdoiMTpZErYKI4-dAwsQG2_nqJBIA0PwLLt6BNrBVFuBFD9MDybyWcwZQs_34XlbynQFO7HvD5TjnZMvEN0n5MZ6JR1rxiuHMIGO9Wng2yq8G0QvTJ8S0sxaSTTtFXIOvtA5lbXN-86401XXsBejLxAL-HtJrktVVdC09_5UxyaLHDoCLSRaiI0Gn78hl9Re4y8wHxfNrqu4eJ_JMUvR0vPc6Pz2k8O8cTwtCYe0F_9uEqyJJgGu8VtevxWd8q-IPC-dHRUc_vqM4PVn_4foT1e6f0RPXLPz-LTAATJZP8yanxXGRin9RiA7UaCAmcDwimoxiGOhrfUcqqxjfkzf8PebxS_hTyeKV8B_lD2ONM-_rMljfjuwjnRzrrBl5vtQ-aiBRdM78fJ92sf32nPzo_nuY0Hh_NEo6h728L8FpN_5HjH3Dyg22YWI8IeO6xjlNfwqktzdnzIWWzD7jHMH3UitCmjjSXEOCIHZwO2M23xRBgukDYpN0qAhMhIA02EpgOLBLd3xc_YlDWLhdNlTebfKMWWGWylLyUWc4Xh4oXK6Eauc6zldpoIWWxL-q8Ltd5vRLZvlmYSnCRc8mlyLIi50sthZCy1tg0us7Wa7bi6JSxS2tHt_ShXRiiASuZZ0WxsEqjpaltC9HhCaaPTIjUxUOVYp700BJbcWso0h-XaKKd-v3PUrJiC4-Vc3Pukw90gdtiB74DcspaDBCwNRQx0HIxBFsdYuwp1YzYMbFrTTwMell7x8QuLXsdnvrgf2MdmdhNmyUmdtNh_g0AAP__yr7mOg">