<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/63037>63037</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            objdump 14.0.3 incorrect disassembly of msr <register, #immediate
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          fozog
      </td>
    </tr>
</table>

<pre>
    The opcode "9f 41 00 d5"   is disassembled as "msr     S0_0_C4_C1_4, xzr" while it should be "msr PAN, #0x1"

See https://developer.arm.com/documentation/ddi0602/2022-12/Base-Instructions/MSR--immediate---Move-immediate-value-to-Special-Register-?lang=en

GNU version properly disassembles the opcode.

I assume this is a problem for all msr <reg>, #imm instructions

How to reproduce:

//create a file msr_imm.s
.text
    msr pan, #1

//compile it with gcc -c msr_imm.s
// disassemble with gnu-objdump -d msr_imm.o -> gives correct disassembly
// disassemble with llvm-objdump -d msr_imm.o -> gives incorrect disassembly


</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyEU8GS2ygQ_Rp06UKFQJLHBx0m43g3h6S24t2zC0FLIgVCBcieyddvYTuJdiu78QEj6Pfoft1PxmjGGbEjzTvSHAq5psmHbvBf_Vj0Xr91f04IflFeIxDO9wPUFTAGuiGcA4CJoE2UMaLrLWqQMYe5GCD_TuzMzi_1-aU614S_wOvXkGHXyVgEkyBOfrUaevwG-uP5U44jXLDXinBO2IGw5_t6QoQppSUS8Uz4kfCjxgtav2AoZXCl8i6febU6nJNMxs_5WxvWMk74kTPOaZV372RE-mGOKawqh0XCjx9Pnyk1zqE2MiGl9KO_4ObgIu2KNHl6WlAZaelnHE1MGCgRRyvnkYgDztt8f_v0F1wwRONnWEJO075txYqQvmtbboEfQMa4OoQ0mZgVlhnfW3Qw-ADSWshaEfEScCTi_UMx4xyYbVEbyt_9FZKHgEvwelWYJdxc3-VUAWVCkDDk9rgYzsa58sFTJnxN923ubE5gkfPj6eonZN4tjy5fTZpgVAqo-jfrPXaryiN6Xqnvv-jVLUD1d5QHSsR7GM0FIygfAqq0Ab_9P6m1F_dLVjP_N-9tLXQn9F7sZYFd1T41TcOrvSimrumlkKoST72q91rvnvZcCdRKNu1OMcEL03HGBWtEVbVNK0Q57Aa9q-u2HQZVK81JzdBJY8ucaenDWJgYV-xawcSusLJHG29O5XzGK9wus0maQxG6W3X9OkZSM2tiij9YkkkWu2-VV3XJSvHzQsEPm9m6zfeP6bo7oViD7f7pw9Gkae0fBsyvPv7oEvwXVInw4y3X7LNbLX8HAAD__yRbajQ">