<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/62995>62995</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [x86] backend (SDAG) asserts: "llvm/lib/IR/Constants.cpp:3071: llvm::APInt llvm::ConstantDataSequential::getElementAsAPInt(unsigned int) const: Assertion `isa<IntegerType>(getElementType()) && "Accessor can only be used when element is an integer"' failed.`
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          joker-eph
      </td>
    </tr>
</table>

<pre>
    Reproduce with ` bin/llc -mtriple=x86_64-unknown-linux-gnu -mcpu="znver4" test.ll` 
[test.ll.txt](https://github.com/llvm/llvm-project/files/11594675/test.ll.txt)

The constant in LLVM IR is: `<2 x float> <float 1.000000e+00, float 2.000000e+00>`.

The LLVM backend seems to assume that the elements in `ConstantDataSequential` are necessarily integers, and `getElementAsAPInt()` asserts.

```
    if (auto *CDS = dyn_cast<ConstantDataSequential>(Cst)) {
      Type *Ty = CDS->getType();
      Mask = APInt::getZero(Ty->getPrimitiveSizeInBits());
      unsigned EltBits = CDS->getElementType()->getPrimitiveSizeInBits();
      for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I)
 Mask.insertBits(CDS->getElementAsAPInt(I), I * EltBits);
      return true;
    }
```

Backtrace below:

```
#12 0x000055d055d80acb llvm::ConstantDataSequential::getElementAsAPInt(unsigned int) const /home/mamini/projects/llvm-project/llvm/lib/IR/Constants.cpp:0:3
#13 0x000055d054a37a4b getTargetConstantBitsFromNode(llvm::SDValue, unsigned int, llvm::APInt&, llvm::SmallVectorImpl<llvm::APInt>&, bool, bool)::$_119::operator()(llvm::Constant const*, llvm::APInt&, llvm::APInt&, unsigned int) const /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:7458:30
#14 0x000055d054933640 getTargetConstantBitsFromNode(llvm::SDValue, unsigned int, llvm::APInt&, llvm::SmallVectorImpl<llvm::APInt>&, bool, bool) /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:7532:11
#15 0x000055d0549e6d56 llvm::X86TargetLowering::computeKnownBitsForTargetNode(llvm::SDValue, llvm::KnownBits&, llvm::APInt const&, llvm::SelectionDAG const&, unsigned int) const /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:38965:9
#16 0x000055d056894438 llvm::TargetLowering::SimplifyDemandedBitsForTargetNode(llvm::SDValue, llvm::APInt const&, llvm::APInt const&, llvm::KnownBits&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int) const /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3561:3
#17 0x000055d0549f726b llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(llvm::SDValue, llvm::APInt const&, llvm::APInt const&, llvm::KnownBits&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int) const /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:44181:3
#18 0x000055d05688b2aa llvm::TargetLowering::SimplifyDemandedBits(llvm::SDValue, llvm::APInt const&, llvm::APInt const&, llvm::KnownBits&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int, bool) const /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:2713:11
#19 0x000055d05688eb09 llvm::TargetLowering::SimplifyDemandedVectorElts(llvm::SDValue, llvm::APInt const&, llvm::APInt&, llvm::APInt&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int, bool) const /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:2951:13
#20 0x000055d056892161 llvm::TargetLowering::SimplifyDemandedVectorElts(llvm::SDValue, llvm::APInt const&, llvm::APInt&, llvm::APInt&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int, bool) const /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3358:9
#21 0x000055d0549eeb5e llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(llvm::SDValue, llvm::APInt const&, llvm::APInt&, llvm::APInt&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int) const /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:43672:9
#22 0x000055d056892d57 llvm::TargetLowering::SimplifyDemandedVectorElts(llvm::SDValue, llvm::APInt const&, llvm::APInt&, llvm::APInt&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int, bool) const /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3460:11
#23 0x000055d056893506 llvm::TargetLowering::SimplifyDemandedVectorElts(llvm::SDValue, llvm::APInt const&, llvm::TargetLowering::DAGCombinerInfo&) const /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:2762:8
#24 0x000055d054a263e8 combineShuffle(llvm::SDNode*, llvm::SelectionDAG&, llvm::TargetLowering::DAGCombinerInfo&, llvm::X86Subtarget const&) /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:42907:9
#25 0x000055d0549f9f86 llvm::X86TargetLowering::PerformDAGCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:58053:36
#26 0x000055d0564d21df (anonymous namespace)::DAGCombiner::combine(llvm::SDNode*) /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2040:16
#27 0x000055d0564d16d8 (anonymous namespace)::DAGCombiner::Run(llvm::CombineLevel) /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1821:18
#28 0x000055d0564d0f9f llvm::SelectionDAG::Combine(llvm::CombineLevel, llvm::AAResults*, llvm::CodeGenOpt::Level) /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:27255:3
#29 0x000055d05677e12c llvm::SelectionDAGISel::CodeGenAndEmitDAG() /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:926:3
#30 0x000055d05677cd5d 
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzsWVtzo7gS_jXKiyouaIGABz8QX7ZcZ3bPVDw1tXVepgS0bW1A-CAxiffXn5KwgyGXSWYn2bNVk0rsIKTu_r6-gNRCa7lViFMSXpFwfiFas6ub6R_1DTaXuN9dZHVxmF7jvqmLNkd6K82OEu7RTCoCy7LM6WVlGrkvkbD5Xcy_8OCyVTeqvlWXpVTt3eVWtfSyyvctYXMC8Kf6ik1AAKhBbSZlaaURb068lIRXx7GJuTMknBOId8bsNWEpgSWB5VaaXZtN8rpyyr-evi73Tf0H5obAciNL1ASWvh8mAY9CAstzoZAcdbnPTzukea20EcpQqeiHD59_patrKq1Ki5OwGdA7uilrYQhbUMJm7n_qTzz3gwSuPI_ArJtDYTjOFoR7k7FKpyYT-Q2qgmrESlNTU6F1WyE1O2Go2SHFEitURlvDCPdmRzvnwog1_rdFZaRw7IkGqcIctRaNLA9UKoNbbLS1SqjCLt6iWXTiUp1-XClDILZc2NVaY2P0wEiLvPt1l5RSKjeUQCxaU1MC6Wy-poTNaXFQX3KhDWGzJ-xjCwLxTDvmIaEkuuplUvrpsEcr79PBiZvN15eELbZo7I2jjWyw4lehb9zcDgZLCUu3aP6DTU0g_nQ4rv_YyEoa-RXX8k9cqStp9FHcA4mtcjlQ0EVp7LyRJUfeeoO-qWEoflM3lrl7LSsn34XMYqTqt7Y6autF2fng23kLe0XgisDV6j6OHR8TqawPjyY8ML13uVsHMyczPeF9aHKDpm0UNU2Lgzskmj8aH93nlchvTCNypBmW9a11zdMhRYD5QL07mythWNi_2BN5Rl1WO68-FVBHjz8Ad8-wtJdJl9iUwHJXV0hgWYlKKklgeSwW-mHxOJUUmRFYrq4JLE9G6Em-3xOWeoSlrIfAziEEgkUiyKgNX9Fs0ZwWW5aXTV39Vhc2hnqI6_lnUbZoXTK0fnbGwxEfH46uK1GWnzE3dbOq9iVhs_EKm3luUVbXZf-ddHMIBF98_3hR77ERpm5OKRI_9EJHJ4H0Jcadj_5ot3TUElj-HvPuc7XG8kN9i41U26OboiCMrafOoi0YuCphjAfe_7ur3pymkAFhqe_3NIVDmpAXIT_D8nvMO8knSd1wXlf71uC_7HPfUVg33bTneOwH79c9Hkmn2BvziiXmRtZqnv4ymPK3hByLEx4SliY9l_ycSx4nQcDiM_sfI3Itq30pN4c5VkIVWHwHmc9R9ty9p53wmKHDsX_v34r7WV3gL2hfNs_dfe-UsRNC7g8rdDSM500EPPt2PP90w_ekQBD48Yj-eJgCcQZCfEcK_LPo7uv3-0Y_RD4blfNkxD9mXvJK_rsn16L8IV544eg_kPsktKHv97EP3qj8g8_9n9y_RdVn7m2vf_KCP3qLwSzE11f9nv0fXfvf3BXvVfEZj2BIPYyjvgijn1H_FlEfcG9Y7YGNuGehx_8m7h_TNU9_mdVVJhU2K7Wp3Zr3f0ZyG7BxT9pwYyiAM4xp3tm53rWbTTnO-K4IpE_vRr6bjdmwSK3bzLiVZyS_-aYwgMSLhjk92hRukk38gk3hR2w2dVP1OF9C4_vFzYvICGMvtO9UjPdsDLd1QQF-0R2OqlodqrrVVIkK9V7keH_ccgbhfsf8HCV_xctPJsSZEads8AJXQ87QRSN0Pi_iV6O7btXoFMnd_YBf8S-ea7wCnB-DeyU7y_V4BM7bJJuncvjc8GfADApieo26dbVzFNZHs-0zxF2_LxMQQRgONmYw3BhEEfqQP8GETYsBilQVi0oapy1-IxBjA45IEuADHMwb4ciLsKCjI-eLYsqKhCXiAqc-j8PA4zGHi900y8INKxB57IdeDFEYRpvIZyyPcMO9DC_kFDxgXsg8z2MBwMRuoXgSIggW5wX3SOBhJWQ5sagmdbO9kFq3OOWQJOFFKTIstWuuASi8pe4mASDh_KKZOmKydqtJ4JVSG91LMdKUrit3F3MSzu-7RQTitSMoOTVuXKcK4NtH18yLbDo8eH7_4BN3qyJ1psnaNa6kFoTNVl1TyrVRXE_osdZKF0ucALeQ0jxHreuG5kLRWpUHmiFtNRb0dofq1B-jUlOhTk0vyy1EdCNkicXE-r5tyumru4jOTzZ2nR__FwAA__-IYwF-">