<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/62744>62744</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Add gfx90a min/max atomicrmw lowering
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          ivanrodriguez3753
      </td>
    </tr>
</table>

<pre>
    Currently, for fmin/fmax atomicrmw instructions on gfx90a, `AtomicExpansionKind::CmpXChg` is returned in both `SITargetLowering::shouldExpandAtomicRMWInIR` and `AMDGPUTargetLowering::shouldExpandAtomicRMWInIR`.

https://github.com/llvm/llvm-project/blob/195621aacb96a4e2f49f5d888e2fc7af20e6e797/llvm/lib/Target/AMDGPU/SIISelLowering.cpp#LL13202C12-L13202C12
https://github.com/llvm/llvm-project/blob/64d169c74d2cd3730893dffacd0061b937e55169/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp#LL5117C6-L5117C6

Does AMD plan on adding support for lowering `atomicrmw [fmin|fmax]` to `[global|flat]_atomic_max_f64` (on gfx90a) anytime soon? I am doing this work as part of my work at Cray and was looking to upstream it. It seems like it would just be adding some more checks/special casing in `SITargetLowering::shouldExpandAtomicRMWInIR` and the code for adding the LLVM IR -> AMDGCN mapping, which seems straightforward. 
</pre>
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