<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/62712>62712</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            *** Bad machine code: Illegal virtual register for instruction *** after early-tailduplication
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          mikaelholmen
      </td>
    </tr>
</table>

<pre>
    llvm commit: c5dede880d175
Reproduce with: ```llc -verify-machineinstrs -mtriple aarch64-none-linux-gnu -o - bbi-63545-aarch64.mir -run-pass early-tailduplication```
Result:
```
# After Early Tail Duplication
# Machine code for function f: IsSSA, TracksLiveness

bb.0:
  successors: %bb.4(0x80000000); %bb.4(100.00%)

  $x0 = COPY undef $x0, implicit-def %0:gpr32common
 B %bb.4

bb.1:
  successors: %bb.4(0x80000000); %bb.4(100.00%)

  $x0 = COPY undef $x0, implicit-def %1:gpr32common
 B %bb.4

bb.3:

bb.4:
; predecessors: %bb.0, %bb.1
 successors: %bb.5(0x50000000), %bb.6(0x30000000); %bb.5(62.50%), %bb.6(37.50%)

  %3:gpr32sp = PHI %0:gpr32common, %bb.0, %1:gpr32common, %bb.1
  CBNZW %3:gpr32sp, %bb.6

bb.5:
; predecessors: %bb.4


bb.6:
; predecessors: %bb.4


# End machine code for function f.

*** Bad machine code: Illegal virtual register for instruction ***
- function:    f
- basic block: %bb.4 (0x9140f00)
- instruction: CBNZW %3:gpr32sp, %bb.6
- operand 0: %3:gpr32sp
Expected a GPR32 register, but got a GPR32sp register
LLVM ERROR: Found 1 machine code errors.
```
So early tail-duplication has changed
```CBNZW %1, %bb.6```
where %1 is a gpr32 vreg into
```CBNZW %3:gpr32sp, %bb.6```
but CBNZW requires a vreg of the class gpr32.

[bbi-63545-aarch64.mir.gz](https://github.com/llvm/llvm-project/files/11475678/bbi-63545-aarch64.mir.gz)

</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzMVk1v4zYQ_TX0ZSBBpERZPvgQb-J2gWw3SBYt2htFjSQ2lKiSVDbpry8o-XsdYLfooYEQ25yZN-89fkk4p5oecU34hvDbhRh9a-y6U88CdWt0h_2iNNXbWuuXDqTpOuVJegOSV1hhUSQVXXKS3JLk5hEHa6pRInxVvg1JJE_mR2sJ0QtaVb9FnZCt6lH1zlsHUeetGjSCEFa2eRb1psdIq358jZp-hMhABGWpojzlGY92WXGnLER27KNBOAcorH6LvFC6GgetpPDK9Ifme3Zu1IH6_PMiSlgKN7VHC3cBC74IpeH2BOyQ9WmmD9JUCLWxUI-9DClQB8kf3dPTDWEf4IsV8tndqxfs0bld_fS_LOPkwAPAjVKic8a6yTLGyzLOCCuS1yKZ_whbkXRzEqJJEodhHiInyACEZa8JkPQWPnx--B3GvsJ6HgycVBcEKR_NozzQaAabsjCve5Fw7HROmv4_SNMfIp0eZ3w_lB2H0g0MFiv8RsvUef5Kdx2uSeaTZH4i-VCWT6H0mhuhKmcx35txVpMuj4ELl3i6l-6Gya6Hnz9em8YD3l7FpWXfaIMPm1_--O2ixSmvcwf5dzh4NhGHyvzfVYaNd9dX0L2_-eLz_N0DG3FeNe1RrbERGl6U9aPQYLFRLuz9gDidS-MMeoCZUaNDu4ACAPV-vBROSSi1kc8nOmBaAiuaJfW8AnbZJy1C9nd5H4EZ0Iq-gmTX4TR7Srl7HVB6rEDATw-PKTvoCmDl6KExfh9zwzE6Fd_f__oJ7h4fPz8G-K0Z-wroud9orbEuvnp-Ppn5EIZwCEcnpzC0woFsRd9gdVF50E1P1Z7jfm3R4pQDyoGASTC8WGxA9d68h_iOk-fYwZK5wuJfo7IYGkzQpgbfIkgdLpcJ53x18c3VGylu_ib8lrCi9X4IC5qwLWHbRvl2LGNpOsK24RrdfUSDNX-i9IRta6XREbalNFvyfFkQtn23w34dLap1Wq3SlVjgmuZFRtNileWLdr1KqKSFkCIvy6JO85qJZSFrkcsVowmVC7VmCUsTTnlSMMbymGa0xpIXPC0rrCtJsgQ7oXQcaMbGNgvl3IjrnC0pW2hRonb7FwY7vRlE5dg4kiVaOe-OZV55jev_ejeCmG7qq7f-YrR6_cP-T_LCBEwK_wkAAP__JByUnA">