<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/62662>62662</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [mlir] Move SPIR-V narrow bitwidth storage emulation to MemRef
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            mlir:spirv,
            mlir,
            mlir:memref
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          antiagainst
      </td>
    </tr>
</table>

<pre>
    We have quite some logic in [MemRef To SPIR-V conversions](https://github.com/llvm/llvm-project/blob/0c7f3d6/mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp) that emulates narrow bitwidth storage support if they are missing in the target environment, like supporting i8 load/store via i32. They are added way earlier when MLIR dialects were not as developed and structured as today. Such logic won't necessary need to couple with SPIR-V; we can use the same mechanism for conversion to LLVM. We should extract them out into a MemRef level conversion for better structure and broader usage. This will also be a nice counterpart to [`EmulateWideInt`](https://github.com/llvm/llvm-project/blob/faafd26/mlir/lib/Dialect/MemRef/Transforms/EmulateWideInt.cpp) we already have there. 

For now we only need to worry about storage; not compute emulation. Specifically, we need to

* Add a MemRef type converter to convert `memref` of narrow bitwidth (e.g., i8) into wider bitwidth (e.g., i32),
* Convert allocation/load/store op size/index and do bit manipulation to get the proper narrow bitwidth value. 

The type converter should be configurable regarding what integer types are directly allowed and what integer types we should use for emulation, like EmulateWideInt. 

Such logic already exists in MemRef to SPIR-V conversions; we just need to generate `arith` ops for various caculations instead of SPIR-V ones. 
</pre>
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