<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/62653>62653</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            X86 crashes when combining shufflevector for <64 x i4>  ("Not a vector MVT!")
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          bjope
      </td>
    </tr>
</table>

<pre>
    Heavily reduced IR:

```
; RUN: llc -mtriple x86_64 -o /dev/null %s

define <64 x i4> @foo(<64 x i4> %0) {
entry:
  %1 = shufflevector <64 x i4> %0, <64 x i4> zeroinitializer, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 64, i32 65, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
  ret <64 x i4> %1
}
```

Running llc command on the above IR (and adding -debug) gives:
```
...
Combining: t208: v64i4 = vector_shuffle<0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,94,95,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u> t218, t207
Not a vector MVT!
UNREACHABLE executed at ../include/llvm/CodeGen/MachineValueType.h:276!
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: build-all/bin/llc -mtriple x86_64 bbi-82399.ll -o - -debug
1.      Running pass 'Function Pass Manager' on module 'bbi-82399.ll'.
2.      Running pass 'X86 DAG->DAG Instruction Selection' on function '@foo'
 #0 0x0000000002dca248 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (build-all/bin/llc+0x2dca248)
 #1 0x0000000002dc7dde llvm::sys::RunSignalHandlers() (build-all/bin/llc+0x2dc7dde)
 #2 0x0000000002dca906 SignalHandler(int) Signals.cpp:0:0
 #3 0x00007f18e52c7630 __restore_rt sigaction.c:0:0
 #4 0x00007f18e2a0e387 raise (/lib64/libc.so.6+0x36387)
 #5 0x00007f18e2a0fa78 abort (/lib64/libc.so.6+0x37a78)
 #6 0x0000000002d4849b (build-all/bin/llc+0x2d4849b)
 #7 0x0000000000876606 (build-all/bin/llc+0x876606)
 #8 0x000000000194ca58 getShuffleHalfVectors(llvm::SDLoc const&, llvm::SDValue, llvm::SDValue, llvm::ArrayRef<int>, int, int, bool, llvm::SelectionDAG&, bool) X86ISelLowering.cpp:0:0
 #9 0x0000000001918aec combineShuffle(llvm::SDNode*, llvm::SelectionDAG&, llvm::TargetLowering::DAGCombinerInfo&, llvm::X86Subtarget const&) X86ISelLowering.cpp:0:0
#10 0x00000000018d1fcb llvm::X86TargetLowering::PerformDAGCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const crtstuff.c:0:0

```

I suspect that `getShuffleHalfVectors` doesn't detect that there is no `<32 x i4>` value type. So either it must be more careful and skip optimizing in situations when the resulting operation wouldn't be legal (or when the value types doesn't even exist?). Or more value types needs to be defined.

Fault was found when experimenting with `_BitInt` types downstream.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzsV1tv2zoS_jX0yyCCRNq6PPjBieM0QNsN4p6ibwEljWye0qRBUk7SX78gdfEl2TbYl8UCJ4gtmuJ8M0N93wzFrRUbhTgns2syW05467bazMu_9R4npa5f55-QH4R8BYN1W2EN94-ELUi8JPHwncb9f_eTXcPjX18JW4CUFVztnBF7ifCSp0_pFK40ELqq8UDoSrVSAqEzewpXYyMUAmE36RReQEwJuwUyjRutCc0vpuksJrQAkl13xqiceR3jA78gAcKWYLdt00g8YOW0uQQPKDcXs7_QaKGEE1yKX2jOFjAa7NiNYBSCrR8kw4AOAzYMpsNgNgzSYZANg3wYFCPgEXrETkbwZERPRvhkxE9GB8noIRldJKMPOvqgx_hHH3T0QUcfdPRBRx909EFHH3T0kY626Wi718Jq9c-v_7tf7HYQl0H3VklJr-Vs-X51CN-PrVJCbUKBqPRux1UNWoHbIvBSHxDuH4HQ3E_zuvYrr2os243X-kYc0B5L0Dl8FEXd4EbvSuF9-DrkaJz76yGdimkoB10deOqrAmE3XgWe_575nvOesZ6rnuGe257Vns9BkkGNQYhBg0F-QXlBdEFvQWpBZUFgQVtBVkFRQUxBR0FCQT1BOEEzhb9b-Lvt__TDbsHRrmY4Gmfdxn7VDni_f_Dl-zdC-yf-19fH28XNp8X151vAF6xahzVwB1FE6EqoSrY1ErqS8rAjdHWja7xDRejqC6-2QuF3Llv89rrHaEvYgmbpCPzw-XaxvgXbljvhfZftBgzutXHgNGyd2wc60BWhq41w27aMKr07uvKXq73Rf2PlfCjWtmgJXYGnVx9YoF5luN1CyaufzvAKeyatHa9-Qt3u9iPp4gjC34PRG8N3wM2m3aFyPg4oWyHrKy4loatSqBDA2zZYluIqp6woIil9T7waGB4cJL2DQSd7bi0Qmq1aVTmhFTz4iS9c8Y3vTJkXz07XrUS_6hSb0KzPg_4HzB95CsvF3RVht8vFHdwr60zbeVmjxDDqXTSDe0KzoSP3tABCWQzxSzz80bridJpDeAhsQdjCvtpu8GCEcmFbv_l9JjQ_LjL8-UlbZ5DvSN9elAstnubv7iyh1_FL74zQ4hhNchFNVtf4XjSPrVqLjeLyE1e1RGP9KeMDDj3emUN6mX4Rp3AGTWjeZ9NN26jae1bF4TMCsR4oa5IcZ7TKUhbD05NB67TBJ-PAig0PTyKq3ppPT80pj5HlGRgurCdH7pMQpe_I_lpFVkdpSImlLM_OEppdADU8y319Nu73QBnPzh9Fer4z03xalH_a37DoDCU7RYnzLE3j9Pco3ZozkPwUJCmmFZ_lsEG37jrBJy6b76G22TNarpeftW9Vyrqelqf3Qu36wOTCGP76iI0_OCrnO-nA7_FSai0vkAYRLhd3ve9uUQE_8vR-jfKzfkYj1OZ9NhXnGSc5x9B0S6Gwz_oi1a_aM3vxxzCON79xs0E3xNHNLRd3XRNGc68a_cbmR56u29IFy5Od_UBWXtxntSbJ66SpynPw92J6QNNoszuG9pHMP5pc0WUBlXHWtU1zqc3fnIfuwbZ2j5UDt-UOSBq_T8k0hlqj9fXYQY1utHBbNAjCgtLemrAbRodTmbc6eDKC8-0V1hpQeAMQDnatdVAi7LRBqLjBppWhMdqfYg9678RO_PLtQiiwwrXcU8DC8xa745pB20rnF-g9mnAXnnUr6y7GEkHihvu3vFybo9kxHnuSER5QAb4I6whbEVpE8C_TRXa6XiHW1rf-EqF7Wayj081c8VY6eOYWGt2qunOKL3s0wjdpH-uzcFu_T0_Xwt0r53doiOVZdd0nmtRzVhes4BOcJ2nOsmKWsXyynTfFjNI8SZM0ntVxxVLO0ywrE-QlL8qymYg5jSmLZ0kSFzFN8qjmjCaYFXWds2RW1mQa444LGXmSRdpsJuFQMk9pOmMTyUuUdnghN_NwfinbjSXTWArr7NHMCSdx7jt4OLtg_2Cq4fB78drbvHn17Qo5fe9Q50-rxaQ1cv7fH7FCQv8OAAD__yGDuMA">