<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/62642>62642</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [aarch64] Double vbsl/vbit/vbif intrinsics with literal masks are converted to and/orr
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          easyaspi314
      </td>
    </tr>
</table>

<pre>
    In certain scenarios, passing the result of `bsl`/`bit`/`bif` to another `bsl`/`bit`/`bif` when using literal masks will result in expansion to `and` and `orr`. It seems to be adjusting the masks (as seen in the ARMv7-A equivalent) but it ends up being too aggressive.

Example code:
```c
#include <arm_neon.h>

uint32x4_t foo(uint32x4_t a, uint32x4_t b, uint32x4_t c)
{
    uint32x4_t x = vbslq_u32(vdupq_n_u32(0xFF000000), a, b);
 uint32x4_t y = vbslq_u32(vdupq_n_u32(0xFFFF0000), x, c);
    return y;
}
```
Expected code: something like
```asm
foo:
    movi v3.2d, #0xFF000000FF000000
    bsl     v3.16b, v0.16b, v1.16b
 movi    v0.2d, #0xFFFF0000FFFF0000
    bsl     v0.16b, v3.16b, v2.16b
 ret
```
Or based on the masked transformation it optimized it to:
```asm
foo:
    movi    v3.2d, #0xFF000000FF000000
    bsl v3.16b, v0.16b, v1.16b
    movi    v0.2d, #0x0000FFFF0000FFFF
    bsl v0.16b, v2.16b, v3.16b
 ret
```

Actual:
```asm
foo:
    movi    v3.2d, #0xff000000ff000000
    movi    v4.2d, #0x00ff000000ff0000
    movi v5.2d, #0x0000ffff0000ffff
    and     v0.16b, v0.16b, v3.16b
    and v1.16b, v1.16b, v4.16b
    orr     v0.16b, v1.16b, v0.16b
    and v1.16b, v2.16b, v5.16b
    orr     v0.16b, v0.16b, v1.16b
 ret
```

This only seems to affect AArch64 mode. ARMv7-a still emits bsl despite the mask transformation.
</pre>
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