<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/62528>62528</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [MCA] Duplicate symbols reported for simple programs (like "hello world") after 98e342dca237
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            tools:llvm-mca
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          ormris
      </td>
    </tr>
</table>

<pre>
    Duplicate symbols are now being reported for simple programs like "hello world" after commit 98e342dca237.

To reproduce:
```
$ cat hello.cpp
#include <iostream>
using namespace std;
int main()
{
     cout << "hello world" << endl;
     return 0;
}
$ clang -S hello.cpp
$ llvm-mca hello.s
hello.s:6:1: error: symbol '__cxx_global_var_init' is already defined
__cxx_global_var_init: # @__cxx_global_var_init
^
hello.s:23:1: error: symbol '.Lfunc_end0' is already defined
.Lfunc_end0:
^
hello.s:31:1: error: symbol 'main' is already defined
main:                                   # @main
^
hello.s:52:1: error: symbol '.Lfunc_end1' is already defined
.Lfunc_end1:
^
hello.s:59:1: error: symbol '_GLOBAL__sub_I_hello.cpp' is already defined
_GLOBAL__sub_I_hello.cpp: # @_GLOBAL__sub_I_hello.cpp
^
hello.s:71:1: error: symbol '.Lfunc_end2' is already defined
.Lfunc_end2:
^
hello.s:81:1: error: symbol '.L.str' is already defined
.L.str:
^
...
$
```

@michaelmaitland, could you take a look at this?
```
commit 98e342dca23729dd4e9cdc5f25c647d617b94283 (HEAD)
Author: Michael Maitland <michaeltmaitland@gmail.com>
Date:   Fri Nov 4 08:51:39 2022 -0700

 [RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV

    On x86 and AArch, SIMD instructions encode all of the scheduling information in the instruction
    itself. For example, VADD.I16 q0, q1, q2 is a neon instruction that operates on 16-bit integer
 elements stored in 128-bit Q registers, which leads to eight 16-bit lanes in parallel. This kind
    of information impacts how the instruction takes to execute and what dependencies this may cause.

    On RISCV however, the data that impacts scheduling is encoded in CSR registers such as vtype or
    vl, in addition with the instruction itself. But MCA does not track or use the data in these
    registers. This patch fixes this problem by introducing Instruments into MCA.

    * Replace `CodeRegions` with `AnalysisRegions`
    * Add `Instrument` and `InstrumentManager`
    * Add `InstrumentRegions`
    * Add RISCV Instrument and `InstrumentManager`
    * Parse `Instruments` in driver
 * Use instruments to override schedule class
    * RISCV use lmul instrument to override schedule class
    * Fix unit tests to pass empty instruments
    * Add -ignore-im clopt to disable this change

    A prior version of this patch was commited in 5e82ee537321. 2323a4ee610f reverted
    that change because the unit test files caused build errors. The change with fixes
    were committed in b88b8307bf9e but reverted once again e8e92c8313a0 due to more
    build errors.

    This commit adds the prior changes and fixes the build error.

    Differential Revision: https://reviews.llvm.org/D137440
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyMV11z6ygS_TX4pSsuCSRbfvCDE493U5Xs7ObOzKsLQdtig0ADyEn-_RZI_siXN65bupGA7nNON93AvVd7g7gk5S0p1xPeh8a6pXWtU35SW_m2XPedVoIHBP_W1lZ74A7B2BeoUZk9OOysCyhhZx141XYaoXN273jrQatnBEJpg1pbeLFOS0Ip8F1AB8K2rQqwqJAVVApO2XxKsjXJVsPzDxuNOyt7gYSNH8ksG_8Nr7QAwQMkB1PRdcfPTBmhe4lA2J2yPjjkLWG_DcO9j8gNb9F3XCD4IAm7HcaUCdByZQitCF2M5ubjIMSfsH2IZgm7-4LbOIBG6pPNtMxh6J2B7PSVzNcXJDQ3e7j59ZlJAVof2ptW8HHMDyPHF7aaEbbKCVsBOmdd_GMIFRA6327F6-t2r23N9fbA3VYZFQidg_LAtUMu30DiThmUg9mvF7AVEMqAFNnX4wPW8reP0Ci7gm36sOuN2KKR2TVEl9NOafDZFcuvuBoi-r2PNM6GQF3_jTKkBd9BKemPWOc_Y51fY10urgX_Hw-_364etlvf19v77Tm1rsX_uzUXKfDdlO9Azq-F5kyU_kwPek2P6rqrqQ_uupc045OD6XR62o9fF6LhWWStEg1H3XIVNDeS0LtYMLSEN9tD4M8IHLS1z8ADhEZ5wjZfGvyiOtKFlAUuhBTljpZiVszlLJ_Xi4JWDAit_vnban2qWatUyiP_xwERPI6QYokaUYYTzCLbt1zpqbDnMrnmAYdNsXEK_mUPUEBWxaSLArMF0IxSuMnm2TsRgJS3T_e_7v4i5ZqUt8fqRco1_OkRHh7_fIB744PrWzTBQ7CxYRyURGitQ-BC9C42nKG1eLAGBnuXTgDgdwOv1QwipdXKiSZq_ev-cQ0qWRdBWeMBjbASgWsNdgehQfCiQdnr2AOU2VnX8jgTlEmjF4vPrlTwqHdT2FgH-Mpjl4ve_lqt19P7fAZ_Z_H17zw9aUovMJiMnqxBaHgA22Ekl1jls5taBVAm4B7d6A01Drr4YB3KCCunVZr4H3C4Vz6g89HRS6NEAxq5TCKi2jfhaFNzgz6u7bjjWqOewh-N8vCsjDzTsrv3CrQdF8FDY18-SpFSd3DziqIPmGR_iYwkdmgkGqHihOik5W8geO9x-kXIUiijCzygizSiJ8kDH_Q5YrgM0jGISYy7X09nGcD3ogHu4RDeOgTrzq4OOhpXBriUKlF4UaH5xOsY2ds-wOPdCqRFD8YGCI6LZ7AOeo9njEOSeDz7OWEZFe54EA3s1OtRjc7ZWmML9VuMdDrPRFaXW0CZYKP3T3oRuoIn7HQ8pZBZdmclPuE-5jWZZQMhMstWhus3r_x56L2FlZRx2tljXJwqweXHR254TMP_u_qamyG657k_d_Nv7jy-n5pIKgPSqcNpf8S5sY6o9yXEHtC5WEPGxMF4pPL-g5QJXQyobnt9YeLHFjbqFXqjAgT0Y-3i3gO2XXi7hPRZmRu1N9bhjWpBaNsll1J5Xmsc8kQ03OzxYwasoHPKOjig8zFfUw07pdkL9-M5etgcJVYUsWRzRvMpUEYZLxBnebYDF_dbwIvdn_bb4BVqTBs2JfqJH-yURj9sZQl1r7Qc2mrKdTyuTWmYEv5s-wUdjshGaHVV1RXL5vVugVD34QQIrBEIfM-VAaxwQUXFcsYzkD1GkWJTOBt-h-KjWGkDjp2Ty1gWGxz1G7D6lI_HzYmX1j4ZW6vdDh2aoLiGJzyoqH_sh00IXTxrELohdOPwoPDFT2Ofm1q3J3Szztm8KLIPfX0il0wu2IJPcJnPIkdWLeaTZpnlsqS0nNFZUVBaVDtkcz7b8bLK5vWc5RO1pBllWZmxfJ7nbD6teM3krigLhouiZiUpMkzt-whiorzvcTmjJa0mmteofbrjURqs1RH8qS1TGm9-bpk-1P3ekyLTyoczo0lQQac74uPdKrbxz3fCq7dAQquvL4KELsa74OUxZ9I7vXyv8V6Fpq_T4YRuIqzxv5vO2f-iCIRuEmFP6CZx_l8AAAD__26ipAE">