<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/62286>62286</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [ISEL]Assertion during lowering vector code with poison
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:X86
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          dantrushin
      </td>
    </tr>
</table>

<pre>
    LLVM fails with assertion during ISEL for this simple test:
```
target triple = "x86_64-unknown-linux-gnu"

define i64 @test(i32 %a) #0 {
entry:
  %v2 = insertelement <16 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, i32 %a, i64 0
  %v3 = insertelement <16 x i32> %v2, i32 0, i64 1
  %v4 = insertelement <16 x i32> %v3, i32 0, i64 2
  %v5 = insertelement <16 x i32> %v4, i32 %a, i64 3
  %v6 = insertelement <16 x i32> %v5, i32 0, i64 4
  %v7 = shl <16 x i32> %v6, <i32 1, i32 2, i32 3, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
  %v8 = and <16 x i32> %v6, <i32 1, i32 -384969324, i32 -1073118976, i32 -2147418112, i32 poison, i32 -384969324, i32 -1073118976, i32 -2147418112, i32 456, i32 -384969324, i32 -1073118976, i32 -2147418112, i32 99, i32 -384969324, i32 -1073118976, i32 -2147418112>
 %v9 = shufflevector <16 x i32> %v7, <16 x i32> %v8, <16 x i32> <i32 0, i32 17, i32 18, i32 19, i32 4, i32 21, i32 22, i32 23, i32 8, i32 25, i32 26, i32 27, i32 12, i32 29, i32 30, i32 31>
  %v10 = sext <16 x i32> %v9 to <16 x i64>
  %v12 = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %v10)
 ret i64 %v12
}

declare i64 @llvm.vector.reduce.add.v16i64(<16 x i64>)

attributes #0 = { "target-features"="+sse2,+sse4.2,+bmi,+sse,+sse4a,+fma,+avx2,+bmi2,+sse3,+64bit,+avx,+cmov,+sse4.1" }
```
Assertion is:
```
llc: LLVM/llvm/include/llvm/CodeGen/SelectionDAGNodes.h:922: const llvm::SDValue& llvm::SDNode::getOperand(unsigned int) const: Assertion `Num < NumOperands && "Invalid child # of SDNode!"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: LLVM.BUILD/bin/llc min.ll -debug
1.      Running pass 'Function Pass Manager' on module 'min.ll'.
2.      Running pass 'X86 DAG->DAG Instruction Selection' on function '@test'
 #0 0x0000000001a8f23c llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /LLVM/llvm/lib/Support/Unix/Signals.inc:606:0
 #1 0x0000000001a8d064 llvm::sys::RunSignalHandlers() LLVM/llvm/lib/Support/Signals.cpp:104:0
 #2 0x0000000001a8d983 SignalHandler(int) LLVM/llvm/lib/Support/Unix/Signals.inc:403:0
 #3 0x00007fb45a25a630 __restore_rt sigaction.c:0:0
 #4 0x00007fb458db6387 raise (/lib64/libc.so.6+0x36387)
 #5 0x00007fb458db7a78 abort (/lib64/libc.so.6+0x37a78)
 #6 0x00007fb458daf1a6 __assert_fail_base (/lib64/libc.so.6+0x2f1a6)
 #7 0x00007fb458daf252 (/lib64/libc.so.6+0x2f252)
 #8 0x00000000008587e3 (LLVM.BUILD/bin/llc+0x8587e3)
 #9 0x000000000095950a llvm::SDNode::getOperand(unsigned int) const LLVM/llvm/include/llvm/CodeGenSelectionDAGNodes.h:922:0
#10 0x000000000095950a llvm::SDValue::getOperand(unsigned int) const LLVM/llvm/include/llvm/CodeGenSelectionDAGNodes.h:1150:0
#11 0x000000000095950a llvm::X86TargetLowering::LowerBUILD_VECTOR(llvm::SDValue, llvm::SelectionDAG&) const LLVM/llvm/lib/Target/X86/X86ISelLowering.cpp:11215:0
```
It happens during attempt to lower BUILD_VECTOR node with freezed undef operand:
```
t102: i32 = freeze undef:i32
t121: v4i32 = BUILD_VECTOR t102, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>
```


</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJy8WF-Pm7oS_zTOixUEYzDwkIds_vSutKen6vZUfYsMmMS3YCLbbNP76a9sExJy0nbvHt2uVmRwPL_565lxmNZiLzlfoOQBJesZ682hU4uKSaN6fRByVnTV98XT0-c_cM1Eo_E3YQ6Yac2VEZ3EVa-E3OPH580TrjuFzUForEV7bDg2XBtElihco3CJaDj8u1fD1J4bbJSwOxFZYwRwyuiOxvNefpXdNzlvhOxP873sEcAA4p4Vr4XkWNAYozh0UiATBDCChCHIMQISYpQ--O1cGvV91APbXS_gRAppzeANb7k0GJFVRPEJCwKIbOyrxTx2QncSwQr_k7fw_0iQzZn29q-cZ8Jrc8krzLVemaLTGEfXKPHrUMjfUOAaJXkdSnzPKHINRF8HlPxNnfgaJXUo-tDc46WWZUiE6Iwzemk0NPqtBNlc6585_ZmsXq3_nGRxTnMCo4vnUZiSKMrylI5LEMVpHGVRBPcz-q0ocUL_KUSevxlh9J31Tj6Evq_rhr_w0nTqnhPTwYm369m9de_r8XRG6UhlIzWqP2oNl-QarYQxvUZOGHMZRuvgIuHCOkogoybkNnGi0JvPT3ePTY5Nd1mn8S23r6Ala5pzIW6alzbwbgwUr_qSB6yqgpeIWnbIpmCDDgjyAVZx45Ec-lDv0_W08JcNU_xtAkdJ_smMUaLoDddDu7AtKH2wbcj3pnnNmekV17b7kLV9woPW3HrZU3Ew0EUrxsXLt8yTdTsQ7OV02X9BIZ6icSHMuNETZdu9XEmLEAC-uGTaUJdjSxb6R023aUpElth2cwRb6z4EWyHLpq_4ZWHVVfwdlwi2z7zhpcVcL9-97yqugwMiy9z6Y4nLTmqDHQ9ZIrJ8Xn9mTc8R0Mmi5fP0nps_j1wxWSHIeukGjwoLaWzLdmgW9mIHouH7vrU5iN_37cBqo0WtDATwKF9YIypcHkRT2SjirsaDRHuiAEHqphZeBd4BH542y-cN1n3RCoMZLvo9VvzYKWOz_WDM0fkOtgi2e2EOfRGUXXtxjf2YH1X3b14a6zqte5sfW1d_B0dic-C4VEwfcMHKr0axkg_inw0rv-Kqb49jhMIAu78Pqtsr1mKm9r3tZPocqODhr8enNYJtIaTToMStkEHT4HnFi37vYaIB5mMvpZ3HjkxbT6XbXroA4g924Q8m2Z4r65ZO4rarejt7QeoBEaSDnvADtC8Zxevluzkim_XyHX6U2qje44-pMoDXZ8EI0nFIS8fiS0IcnsLzX8SyGkh5lTf6u_bEByWkcX77ZB2JILtsUuzbrtNGcdaioSD6ZEKwneZ4Iwqbzv3RhhrB9i8pTnZB7CVrdCCkPRc0pIgsw4uO0Y2OVUjjezp-7KVH-heTVcOVtrUHcvxzHc7Cy6PNhiiMp8LhVnieETwRY4deb-8bjI1DMpVHBnlpXcQJg4RREuLdTnFtOsV3ymAt9szFNCgd64Q9vmbPqoKSLMWKCW0TLPNa2aJsP8tAdwFF8BCeiN136QEISHIDlLI0w6ywR_SnQHbfBIhOgVgdMYp3O3912dmysCvYL9QDyzRBTW9RIYFfQEACE4jsOrJhlmQpJxbi_ml3IH7TBCWfoORJnoTszYX3lS3hZ_1gyAV7bMJfqeYbxe_QLYqScKpc9HPlvmT0k2v_T903bq-2ftm9udjsPm9Wn_78OClEY-tbXZt5pZArT_ft8afVy0Sw_ZJR_3x85s1Zh3ONiCBKrqyZNvdHgw_seORSny_lzBjeHl1raywSvjYAy67i_jZfK87_wyvcy4rXuBvC8aOLexS69u-uZmQ9MHteRJZ2ghz2QWT3vcTnnRPpDgZWeGVdwqQZWMnqfJ_9H7-4p6p_zqoFqXKSsxlfRDSDMM9zkswOi6KKSJGEWR6XQEmSc8IL4EkZZXUMcVrPxAJCIGEMUZQmWZIEOatrxkNC0yomNYtRHPKWiSZwk2in9jM3ESwoQEZnDSt4o90vKwB2FODOqy7CgJL1TC3cPFH0e22nWaGNviAZYRr3s8zj8-YJJevl7U8uzZAceLi5lGM8_UVt1qtm8faRxtnw3wAAAP__NlL8HA">