<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/62060>62060</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [Wrong Code][inline-asm] output operands overlap with output
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          youngbe
      </td>
    </tr>
</table>

<pre>
    For code:
```c
#include <stdint.h>

struct Test
{
    uint64_t var1;
    uint64_t var2;
};

void ppp(struct Test *tt)
{
    __asm__ volatile (""::"a"(tt):"rdi");
    uint64_t temp;
    __asm__ volatile (
            "movq   $0, %0\n\t"
            "movq   $1, %1"
            :"=r"(temp), "=m"(tt->var2)
            :
            :);
}
```

After compile:
```as
ppp:                                    # @ppp
    movq    %rdi, %rax
    movq    $0, %rax
    movq    $1, 8(%rax)   # %rax overlap, abort
    retq
```

clang version is 16.0.0.

gcc works properly.

According to gcc's doc, an output operand will only overlap to input operands:

> Use the ‘&’ constraint modifier (see [Modifiers](https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html#Modifiers)) on all output operands that must not overlap an input. Otherwise, GCC may allocate the output operand in the same register as an unrelated input operand, on the assumption that the assembler code consumes its inputs before producing outputs. This assumption may be false if the assembler code actually consists of more than one instruction.
> 
> The same problem can occur if one output parameter (a) allows a register constraint and another output parameter (b) allows a memory constraint. The code generated by GCC to access the memory address in b can contain registers which might be shared by a, and GCC considers those registers to be inputs to the asm. As above, GCC assumes that such input registers are consumed before any outputs are written. This assumption may result in incorrect behavior if the asm statement writes to a before using b. Combining the ‘&’ modifier with the register constraint on a ensures that modifying a does not affect the address referenced by b. Otherwise, the location of b is undefined if a is modified before using b.

from https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html .

</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyUVk1v67gO_TXKhqjhyPlcZJEmzVs9vM19mGUhS0ysGUvKlejk5t8PKDtfnfQCExiuLYqH5OERa5WSPXjElZi-i-l2pDpqQlxdQucPNY7qYC6rXYigg0FRrUW5FeVazMr-0sO7rKzXbWcQRLVJZKynohHVx2DO90Sx0wQ_MNGwPH_vHwAAOutpNvkkOKk4FtU3FnmziPn2_pzvp2ANHI9HIRcPoUDINZGQyxcxPz9Vcp-fcAqtItsiCLkQUvJVrfmSUuX3RY-QV6KxeW35OklCd3yyvAxys15_QkoXTj_z06QUcgNCTksx3Xgx3RAH_L3LeHAZv96aMxfVNg7lcJJy2fvwuruW-Saqj8zzlbCvMK-xl099edbIY4_We0LWkjva9oWcVOoXuIvVU5TvfkJWICYlO9wyG1hhOnKzMjFR_Xq148b1d_ZM7CILI--Ry2vU_A7hhLFVR96l6hDpDhKRfv6GCt0qf4ATxmSDB5tgPCvKoiwe9xy0hnOIfyU4xnDE2F6ezGutQzTWH4ACHLQWcp7ABJ2T8RA6OnYE7Ki8gbNtWwi-vVxzZi_rH7ake0f6e_UB_08I1CCIDykWpVguhJxdn5egg08UlfUELhi7txhZ3wkRxPT9v8NSEtOtkIuG6JhDyJ2Qu4PWxcF3RYgHIXfBt9ajCTr1JiF3N--iIdcKWd3hWLpLCB4Ul_RUZgJqFIHrEoEPdKtV-b7WAv5HDcazTcg0_WezAacuDBS0or7WL8RZn1eTcggRDzaxhlViyM5HbBWheSaSkUPvpVLq3JFsflV0XUNXt9hP1Uxi5zCBpdTjJKhxHyJy202nucN9TqmAH41Nj6icfY2wV21CsPtXAZSmTrXtJUeyiRKEPTjGp4Z14hGs72emDb64N__-9ONKwDGGukUHmh217iLHZISBtKOKyiH1OlDcJqb2nEDduXtQDfOrfOCWvESonxAcuhAvD_5FTiwXeUCPMbeivuS2UgClNaaUKRlclTGRl6yHOteggydl_S25BOfG6gacPTTExKZGxR5U9efKZPRMpeH91ISED_4U2G3oI4WhIa6AdeIRcbrpLjcRB8GmTjeDiO5QKt7UYa6SUP5yFUO2n6MlQv9aGBFT1xJXa70OMaLmmhp1siHexeIgkSJ06CnDYc5bXSN2iQVYF7AJrrY-z5tvJ8JtDJwtNXnfq7bz0QX0qYvX-rPfhbEVmIApH16133PGOcuhcRH3GNHrviX1l-PMO_NBZgLCHmoerJ03uOfpwhUrXhmSNF8rfBx--xgc_MuR9fGL0Bs0b-vk8tSCAXJkVpVZVks1wtV4thiPl4uqGo-aVa2NnNd6rsZ1XZWqlrLa42K5ULOp2avZfGRXspRVORmPy3klx-NiPJuriZqUsqylKo0UkxKdsm3RtifHqY1sSh2uZrKclaNW1dim_HEnpcczZCP_t59uR3HFPm91d0hiUrY8Ge4oZKnNX4V_xOAPsOHvv-lWTN9trvtNJSem239M3-u8ze3vjaMutqsvTFpqurrQwQm545DDn7djDH-iJiF3OVGmNhfydwAAAP__nQlStw">