<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/61619>61619</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [ARM] `AddrMode6` operands with register offset contain additional immediate 
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Rot127
      </td>
    </tr>
</table>

<pre>
    If an `AddrMode6` operand is decoded and the offset is given in an register (instead of an immediate), an unnecessary immediate operand is added to the disassembled `MCInst`.

Here is the code in question:

https://github.com/llvm/llvm-project/blob/7949a2a802f0791eaf7c6ecbdd6ed5daa2a278cf/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp#L2944-L2952

The decoding of `AddrMode6` operands always adds an immediate. Independently if there is one encoded in the instrucion or not.

This way the disassembled instruction is inconsistent to the defined instruction in the `.td` files.
The `MCInst`'s operand count is no longer the same as its corresponding `CodeGenInstruction`.
Which is a problem if the disassembled `MCInst` is used with generated code from `TableGen`.

**Minimal reproducable example**

- Set a breakpoint at the code above.
- Disassemble the `ARM_VLD2d32wb_register` instruction: `vld2.32 {d20, d21}, [r0], r6` (little endian: `0x864860f4`).
- See how an additional operand is added although it is not encoded in its opcode nor listed in the `In/Out OperandLists`:

Opcode of `ARM_VLD2d32wb_register` (as given by `CodeGenInstruction->TheDef->dump()`):
```
VLD2d32wb_register {    // InstructionEncoding Instruction InstTemplate Encoding InstARM NeonI NLdSt Sched
  field bits<32> Inst = { 1, 1, 1, 1, 0, 1, 0, 0, 0, Vd{4}, 1, 0, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Vd{3}, Vd{2}, Vd{1}, Vd{0}, 1, 0, 0, 0, 1, 0, Rn{5}, Rn{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0} };
...
  dag OutOperandList = (outs VecListDPair:$Vd, GPR:$wb);
  dag InOperandList = (ins addrmode6align64or128:$Rn, rGPR:$Rm, pred:$p);
...
```

</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyUVl1vozoT_jXOjVUEhhC4yEXSbPaN1G5X2arv5crgAXwO2BzbNNt_fzQmadyviyNFhDHjZ76eGZtbK1sFsCbLLVnuFnxynTbro3YJWy0qLV7Wh4ZyRUkeb4Qw91pATvKY6hEMV4JKSwXUWoCgKLoOqG4aCw6_tPIZFJUKAQy00jowlLBCKuuAC6o9tBwGEJI7IKwk7BaXJqWgBmu5ebl-Dm1ygRad9gaFtNxaGKoeBDp6f3tQ1pE8jki8I_Fmfv4PDOBW3IEOo1__TGCd1Iqkm1C1c260uMb2hO1b6bqpimo9ELbv--fL381o9F9QO8L2Va8rwvarMis540XMmnhVJsCbVZ1DXQmRg1gKzhlnq6JuAhyJ-x65aQFxNsd7wva7azxmXgxXonocCUvvWJllN3esXLLQ9UfMBxZEqhbz-0XdLOX9ib_4RNo3RYjoQQkYQQlQrn-hssGMzanTCiioudpS-UxiKc1US62oNlRpF731Rlp64i8fy3Teh8lHZKlqrSwSRLnXskIj1XvV2SrW1gmMp5E92Ogae1h-wlb2lTS1npQnpdK016oF45EsH4ByS6WztNbGgB218skjeXyrBXwHdbg6cCXV_ztZd56KdDS66mE4p-prOqL2ZEHQk3QdbUGB4Q7EzMbG6AG1H3nVo9H39CUMf_dSyYH31MBotJhqVKbwhw9jD7NGuOeG_gJHOa0M8L9HLZWj3F0bgFf6GaKLasCxS443x_vfT3c7JlJ2qn5fOthHEqQk3aDucy9YlDJKVlvBYuxjwRKy2uEbWW5NTJb-3XgaElb00jl0XgnJLyDxnyLPijxuMl--MrrGAbTTJ2QqF0KiXd5_HAi8d52e2o7Kc6ldyFessR596Eob2mM0IqDUQRG2f5gcfZhx76R1Fh15Ox0eZohzc32ZIsIKfhmB1cvndLoh6bfHDnbQ4JuYhpGwAsegj_5qN4_PPy9-tIdZJ3E5zysaGPimzqMgWPPvjzCMPQ7VNxqb4z39AVod6I878cvRX3UHYjZKaSOhF7SSzpL0NmUk_eb3UJLu0D5NsLzvHvHbt-vjSZDVNjvz46pwVGS1Tc_LXmChkIRCfBY8VBoKLBSSUIg_WIw_cdPDL0NbF0-PQ-jfEPo3hP4NZ1sUF9LtnMIoii65FLylD5MLiDankRV6cpY-QY1ru59cGn8OZU8Ccb__PM7iqfL82IZ4B_UJnFS-N8yABwDvZavyTJuEFTPOUfmefMU9DiiPBsQsj6GZV__f8XEh1qko05IvYJ3kqzIryiTJFt1asHJZA89jWJZNnUOR8qpZrqq44iJpWL2QaxazNE4ZS1i2TJII0jpOMs7TsknTsihJFsPAZR_heRlp0y6ktROs8yRPykXPK-itv7swpuBE_UfCGF5lzNof0tXUWpLF2Oz2iuKk6_2lB0_c5e7rY9KP6tc2O19taq0cl29G0fWWsphMv_7PNwjvuSVs7yP7NwAA__-p3e2N">