<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/61621>61621</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AMDGPU] Disassembling 16bit VOP1/2/C instructions fails
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          DadSchoorse
      </td>
    </tr>
</table>

<pre>
    LLVM version: 3a3ad9fe1811ebd7ff865b77f471d155d9a05ec8

Example input: `6a040381` which should be `v_mul_f16_e32 v2, v1, v1, opsel: [1, 0, 0, 0]`

Current output: `v_mul_f16_e32 v2, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v1 ; Error: VGPR_32_Lo128: unknown register 145 ; 6a040381`
</pre>
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