<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/61430>61430</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [GlobalISel][AMDGPU] machine verify error: VOP* instruction violates constant bus restriction
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            globalisel
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          chenzheng1030
      </td>
    </tr>
</table>

<pre>
    This is from https://reviews.llvm.org/D141247, with that patch, there are some AMDGPU cases crash because of machine verify error. Below is a reduced case from `llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir`.

To reproduce this error, first need to do some change in the td file:
```
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 70e50111790b..80d95fb0ad01 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -263,7 +263,7 @@ let SchedRW = [Write64Bit] in {

 def : GCNPat<
   (i32 (DivergentUnaryFrag<sext> i16:$src)),
-  (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10))))
+  (i32 (V_BFE_I32_e64 i16:$src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10))))
 >;
```

And then we get LIT failure for case `llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir`:
```
# After InstructionSelect
# Machine code for function zext_vgpr_s1_to_vgpr_s16: IsSSA, NoPHIs, Legalized, RegBankSelected, Selected

bb.0:
 %0:vgpr_32 = COPY $vgpr0
  %2:vgpr_32 = V_AND_B32_e32 1, %0:vgpr_32, implicit $exec
  %5:sreg_32 = S_MOV_B32 16
  %4:sreg_32 = S_MOV_B32 0
  %3:vgpr_32 = V_BFE_I32_e64 %2:vgpr_32, %4:sreg_32, %5:sreg_32, implicit $exec
  $vgpr0 = COPY %3:vgpr_32

# End machine code for function zext_vgpr_s1_to_vgpr_s16.

*** Bad machine code: VOP* instruction violates constant bus restriction ***
- function: zext_vgpr_s1_to_vgpr_s16
- basic block: %bb.0  (0x2b23ba70)
- instruction: %3:vgpr_32 = V_BFE_I32_e64 %2:vgpr_32, %4:sreg_32, %5:sreg_32, implicit $exec
```

The error can also be reproduced with below mir source:
```
name: zext_vgpr_s1_to_vgpr_s16
legalized: true
regBankSelected: true
body: |
  bb.0:
    liveins: $vgpr0

    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s1) = G_TRUNC %0
    %2:vgpr(s16) = G_ZEXT %1
    %3:vgpr(s32) = G_SEXT %2
 $vgpr0 = COPY %3
...
```
```
llc -march=amdgcn -run-pass=instruction-select -global-isel inst-select-zext.mir -verify-machineinstrs
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJy8Vl1vozgX_jXOzRHI2ECSi1zko_StNNNW007n3b2JDBzAOw5Utkk78-tXBpKQ2US7mh2tZCVgP5zz-HwLY2RZIy5ItCLRZiJaWzV6kVVYf6-wLgPK6SRt8m-L50oakAYK3eygsvbVEL4kLCEs0biX-GZ8pfY7v9ElYckmCAMWTglbw5u0FdhKWHgVNqvclq1QIwiNYJodwvLj5vbxM2TCoIFMC1NBiploDUJTwE5klawR9qhl8Q1Q60b7sELVvDk-AjTmbYZ5931Pj8TUcSEssWgsYcm6yfEWa8KSXhdhya1qUqHunlARlsjaWM-gwsx63_Hd-jupSUx9QjeELvvf5wY0vurGKQPrrNFRcfcppDYWasQcbAN5018rq0RdIsja3RdsDoVU6IzWC43psLrXXBYFeF4pLQjCkoG-kilhybPQJdox-ZeHR35XG6vbzMqmNr7NIf2pz3rtss7xHaYUIxoEwXROU9-f0XweFSkVOQ0goDQOwx7sed5Pchxuzlb9-leUSUhJSMFjMSdsPQXCVsfH_kihhaeswvzTFyB8AyRafdHSYhyupCXRxnmGTFdjH0OOBRC-hNv1_aOwhK-HfQDCZpIz97eRe9Ql1vZzLfS3RIuS8LXBd0v4Dcgg7vIiNDojbN6tQYg3FvKyXSU32zvOthiHcMCv3dHT9uPDy3bV4xycHgVdPn4PjohuHax8Xd85y1-oFQi_IXx1McT732Wdu3yo4Q2hRAsf7p6hEFK1GqFodJ_FvyqBr2UbYRyWhUUNo9h66j4_AT4OhSdr8p5a0dYdEJyG7b581VsTbG1zeHQ2hTvz9LR0RrtvHv93Z9zTByyFkt8xdy-fsFyJ-muvrN86Po_MlKb-iT0QFrm3To9zAd_A-uHxNxc3bo8eopSwiP2Ae9ku7zfOcVvkDILenWNpbkfuXpXMpHUC8R2zkbyI8KXRWB7knQIhiEew8CpsTI7_hdx5FozZD0xHgoed6HznOvfeNmNrjQmMre3cfVPnx17zz13un4sZFqzEuTAXGS8Pj-5IniIO9rJRwrqu19TGitpC2hrQaKyWPeIo8lBDDoycxKtxOGBTYWQGqWqyrw5OWOTCqisL9J2ljKdiSo-5642pDfj_zmEXi8VzhX2XhUzUIJRpIMVTG8774SLtZoGd1GCaVmdXe2wtdvj3ZlPHbOVLsLrFflv_kLdnh25C6iw2PTaM8wQGACX3KGvTG3actifIKDEJmxlnrvn1ZO_wwQgfHOC32-dPn--HRB-j2Rgdn-C_3_z_uZc2RvOLXG63TwOaHavTxUzrDn3fv-zf81elMvB2QmcV4Ruxy8usBk-3tfcqjCF8M4rMocyDV3YNwJMGFVyq_-D1I6M3JGInw_ygfpIveD7nczHBRRBPZ7NpwFkwqRZFFkdRjmEa0TQO4xizGS-mM0bpbM4E5RO5YJRxyoOIzuksDPyMFVzkTGTTaFbQeEZCijsh1XEunkhjWlzEQcjpRIkUlenmbsb6q7ibEMbcHK4X7iMvbUtDQqqksafxemKlVd3EPmqB0YZEq6E3RpuLQ_PP1qBJq9XifOIvpa3a1M-a3WiCc4RfdfOHa6Is6e5qCEu66_4ZAAD__9R2m5A">