<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/61384>61384</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [X86] Incorrect encoding for ATOMIC_LOGIC_OP
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:X86
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          omern1
      </td>
    </tr>
</table>

<pre>
    In https://reviews.llvm.org/D140939 the following encodings were introduced for the `bts`, `btc`, and `btr` instructions:

```
multiclass ATOMIC_LOGIC_OP_RM<bits<8> Opc8, string s> {
  let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
      SchedRW = [WriteBitTestSetRegRMW]  in {
    def 16rm : Ii8<Opc8, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),           -------> Type Ii8
 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"),
 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR16:$src2))]>,
 OpSize16, TB, LOCK;
    def 32rm : Ii8<Opc8, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),           -------> Type Ii8
 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"),
 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR32:$src2))]>,
               OpSize32, TB, LOCK;
    def 64rm : RIi8<Opc8, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), -------> Type RIi8
                   !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"),
                   [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR64:$src2))]>,
 TB, LOCK;
  }
}

...

--- Incorrect base opcodes for 8 bit immediate (https://www.felixcloutier.com/x86/bts. https://www.felixcloutier.com/x86/btc, https://www.felixcloutier.com/x86/btr)
defm LOCK_BTS_RM : ATOMIC_LOGIC_OP_RM<0xAB, "bts">;
defm LOCK_BTC_RM : ATOMIC_LOGIC_OP_RM<0xBB, "btc">;
defm LOCK_BTR_RM : ATOMIC_LOGIC_OP_RM<0xB3, "btr">;
```

As shown above, the ATOMIC_LOGIC_OP_RM defines the instructions as taking an immediate operand but uses the MR base opcodes.

I've created the following patches to fix this issue:
https://reviews.llvm.org/D145930
https://reviews.llvm.org/D145933
</pre>
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