<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/61084>61084</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [SPIR-V] LIT tests failing with LLVM_ENABLE_EXPENSIVE_CHECKS enabled
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:SPIR-V
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            michalpaszkowski
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          michalpaszkowski
      </td>
    </tr>
</table>

<pre>
    Current issues:
Issue | Total failures | First passes to fail | Phabricator reviews/Pull Requests
-- | -- | -- | --
Pass modifies its input and doesn't report it | 5 | SPIRVPrepareFunctions | https://github.com/KhronosGroup/LLVM-SPIRV-Backend/pull/252
Illegal virtual register for instruction | 102 | Post-RA pseudo instruction expansion pass, SPIRV pre legalizer |  [D144897](https://reviews.llvm.org/D144897)
Virtual register does not match instruction constraint | 1190 | SPIRV pre legalizer, IRTranslator |  [D144897](https://reviews.llvm.org/D144897)
store memory size cannot exceed value size | 3 | SPIRV pre legalizer |  
inconsistent constant size | 66 | SPIRV pre legalizer |  
bitcast must change the type | 34 | SPIRV pre legalizer |  
Expected a register operand | 28 | SPIRV pre legalizer, IRTranslator |  
Virtual register defs don’t dominate all uses | 29 | IRTranslator |  
G_BUILD_VECTOR result element type must match source type | 4 | IRTranslator |  

Solved:
</pre>
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