<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/60865>60865</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
Redundant low-bits masking of 64-bit register in AArch64
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
aqjune
</td>
</tr>
</table>
<pre>
From this input:
```
define i64 @f(ptr %0) {
entry:
%x8 = load i64, ptr %0, align 4
%x9 = lshr i64 %x8, 32
%x8_2 = and i64 %x8, 4294967295
%x0 = mul nuw i64 %x8_2, %x9
ret i64 %x0
}
```
`llc --mtriple=arm64-unknown-unknown -mcpu=neoverse-n1 -O3` emits the following AArch64 assembly:
```
f: // @f
ldr x8, [x0]
lsr x9, x8, #32
and x8, x8, #0xffffffff
umull x0, w8, w9
ret
```
But I think `and x8, x8, #0xffffffff` is redundant because `umull x0, w8, w9` will already use the low bits of `w8`.
https://godbolt.org/z/qaaPe8M5K
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyElG-P4yYQxj_N-M3IEQFM7Bd-kb0oUlVVrfoFTtjGCbcYcvw57_bTV9i-ZFNtWxQJhfk9M8MzJDIEfbFKtVC9QHUqZIpX51v5_Vuyqujc8N6evZswXnVAbW8pAjsCOQE5giDbZ_k6qFFbhVpwBE5GoPUtegRaEaANwuFlxZSN_v2eAzPwViOwExonhywH-gUf0i8ojb5Y5B8FzSoIV7_WyzkyyuhT2q904aQdnjFOG96IA22qjzhZ4CkZtGl-CL7SLFmqbrRX8R7eLg-H06em3A-N6bEsp-j1zShgJ-knwctkX62b7c8dy6m_JWAnq9wP5YMq7R7L3xkIgmrSMWC8KhydMW7W9oLHo--vgqMMQU2def-30YzAjgj0DPS8zma79brM4Jd99QaqlzcC1XYdNGELNjm4IZQ9jF5XtviR446Rt3Fbz3iakjH4tox3XuC5eSa8iv9h6EuK-Et-k_YVQZD_ry4I6oBeDckO0kbsVC9TUFn8aS-C4KyNQWm8ksM7ZjZ7b9yMXR6EG7N2rkGQ3cfOrjHeQp7D4vbFDZ0zcef8Bej5L6Dn71L-oerfql9XvBhaNjSskYVq9-IgalEzVhXXlu-JlLWs5Sg5P_S8YhWvWK96NnTNKHihW0ooI5QSwnN0Vx8GXu1HoThrJNt3wImapDY7Y35MuYNCh5BUK0gtqsLITpmw_OoptWrGJQiU5j8B32ZN2aVLAE6MDjE8skQdjWr_vFtp3FwulkwyvOZX6UYUPB-hVxcdovKo7c-3WiRv2n-YpOM1dbveTUDPucy2lTfvvqk-Aj0vzQWg56X5vwMAAP__wjpQxw">