<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/60562>60562</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Incorrect lowering for SVE predicate permute builtins.
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AArch64,
            clang:codegen,
            SVE
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          paulwalker-arm
      </td>
    </tr>
</table>

<pre>
    When lowering predicate permute builtins we incorrectly assume only the typically "active" bits for the specified element type play a role with all other bits zero'd.  This is not the case because all bits are significant, with the element type specifying how they are grouped:
    
b8  - permute using a block size of 1 bit
b16 - permute using a block size of 2 bits
b32 - permute using a block size of 4 bits
b64 - permute using a block size of 8 bits
    
The affected builtins are svrev, svtrn1, svtrn2, svuzp1, svuzp2, svzip1 and svzip2.
</pre>
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