<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/60463>60463</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] DAGTypeLegalizer error when lowering llvm.vp.reduce.fadd.v1float
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            bug,
            backend:RISC-V,
            vectorization
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          dcaballe
      </td>
    </tr>
</table>

<pre>
    Hi all,

We (IREE@Google) are hitting a gap in the RISCV backend when lowering a masked vector reduction for a vector of size 1.

repro.ll:
```
declare float @llvm.vp.reduce.fadd.v1float(float, <1 x float>, <1 x i1>, i32)

define float @test(float %s, <1 x float> %v, <1 x i1> %m, i32 zeroext %evl) {
 %r = call reassoc float @llvm.vp.reduce.fadd.v1float(float %s, <1 x float> %v, <1 x i1> %m, i32 %evl)
  ret float %r
}
```
`llc repro.ll -mattr=+m,+a,+f,+zvl512b,+zve64x -mtriple=riscv32 -target-abi=ilp32 -riscv-v-vector-bits-min=512`

Error: 
```
LLVM ERROR: Do not know how to scalarize this operator's operand!
t68: f32 = vp_reduce_fadd ConstantFP:f32<0.000000e+00>, t64, t66, Constant:i32<1>
```

It looks like this is hitting a switch without support for vp intrinsics in `DAGTypeLegalizer::ScalarizeVectorOperand`. I'm not sure if for this particular vector length, the vp intrinsic should have been replaced with a scalar implementation before `DAGTypeLegalizer`. This seems to work for x86 because the vp intrinsic has been replaced before this point.

@topperc, @preames, @rofirrim, @asb 

Thanks!
Diego
</pre>
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