<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/60424>60424</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
Failure to merge equivalent comparisons/switch cases
</td>
</tr>
<tr>
<th>Labels</th>
<td>
missed-optimization
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
RKSimon
</td>
</tr>
</table>
<pre>
https://simd.godbolt.org/z/qW4so9Mbq
```C
#define CASEA 34
#define CASEB 36
#define CASEC 0
#define CASED 127
int testSwitch(int a0, int a1, int a2, int *out) {
bool addOffset = a0 == CASEA || a0 == CASEB;
switch(a0) {
case CASEA:
case CASEB:
*out++ = a1;
break;
case CASEC:
case CASED:
*out++ = a2;
break;
default:
*out++ = -1;
break;
}
if (addOffset) {
*out++ = a1 * 9;
}
return a0 + a1;
}
int testIfElse(int a0, int a1, int a2, int *out) {
if (a0 == CASEA || a0 == CASEB) {
*out++ = a1;
*out++ = a1 * 9;
} else if (a0 == CASEC || a0 == CASED) {
*out++ = a2;
} else {
*out++ = -1;
}
return a0 + a1;
}
```
Reduced from an internal code snippet - the 'addOffset' boolean is the same comparison as the CASEA/CASEB in the first switch (and the IR converts it into a second switch) - but its still tested separately.
```ll
definei32 @_Z10testSwitchiiiPi(i32 noundef %a0, i32 noundef %a1, i32 noundef %a2, ptr nocapture noundef writeonly %out) {
entry:
switch i32 %a0, label %sw.default [
i32 34, label %sw.epilog
i32 36, label %sw.epilog
i32 0, label %sw.bb2
i32 127, label %sw.bb2
]
sw.bb2: ; preds = %entry, %entry
br label %sw.epilog
sw.default: ; preds = %entry
br label %sw.epilog
sw.epilog: ; preds = %entry, %entry, %sw.default, %sw.bb2
%.sink = phi i32 [ -1, %sw.default ], [ %a2, %sw.bb2 ], [ %a1, %entry ], [ %a1, %entry ]
store i32 %.sink, ptr %out, align 4
switch i32 %a0, label %if.end [
i32 36, label %if.then
i32 34, label %if.then
]
if.then: ; preds = %sw.epilog, %sw.epilog
%out.addr.0 = getelementptr inbounds i32, ptr %out, i64 1
%mul = mul nsw i32 %a1, 9
store i32 %mul, ptr %out.addr.0, align 4
br label %if.end
if.end: ; preds = %sw.epilog, %if.then
%add = add nsw i32 %a1, %a0
ret i32 %add
}
```
(https://alive2.llvm.org/ce/z/Te8JKK
</pre>
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