<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/60378>60378</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            TableGen generate RegMask doesn't contain Alias Register result in liveRegUnit analysis problem
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          emelife
      </td>
    </tr>
</table>

<pre>
    Version: LLVM 12.x  
1. CSR Register mask doesn't contain alias register  
```c++
    // Emit the *_RegMask bit mask of call-preserved registers.
    BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
    ...
    OS << "static const uint32_t " << CSRSet->getName()
       << "_RegMask[] = { ";
    printBitVectorAsHex(OS, Covered, 32);
    OS << "};\n";
  }

BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
  SetVector<const CodeGenRegister*> Set;

  // First add Regs with all sub-registers.
  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
    CodeGenRegister *Reg = getReg(Regs[i]);
    if (Set.insert(Reg))
      // Reg is new, add all sub-registers.
      // The pre-ordering is not important here.
      Reg->addSubRegsPreOrder(Set, *this);
  }
 ...
}
```  
tablegen generate regmask only search register's super and sub register, doesn't search it's alias， so that alias register doesn't be masked  

2. XXXRegUnitRoots combines all alias register as one unit in it
```c++
extern const MCPhysReg HiIPURegUnitRoots[][2] = {
...
{ XXX::Xhf21, XXX::Xyf21 },
...
}
```   
Xhf21 and Xyf21 are alias, they all belong to X21

3. LiveRegUnits Problem
```c++
void LiveRegUnits::removeRegsNotPreserved(const uint32_t *RegMask) {
  for (unsigned U = 0, E = TRI->getNumRegUnits(); U != E; ++U) {
    for (MCRegUnitRootIterator RootReg(U, TRI); RootReg.isValid(); ++RootReg) {  // Here checks all regiters of one unit if it is masked in regmask.
      if (MachineOperand::clobbersPhysReg(RegMask, *RootReg))  //  In my case  Xhf21 is masked but Xyf21 is not. so that reset X21 is and result in LiveRegUnit incorrect.
        Units.reset(U);
    }
  }
}

void LiveRegUnits::stepBackward(const MachineInstr &MI) {
  // Remove defined registers and regmask kills from the set.
  for (const MachineOperand &MOP : phys_regs_and_masks(MI)) {
    if (MOP.isRegMask()) {
      removeRegsNotPreserved(MOP.getRegMask());
      continue;
    }

    if (MOP.isDef())
      removeReg(MOP.getReg());
  }

  // Add uses to the set.
  for (const MachineOperand &MOP : phys_regs_and_masks(MI)) {
    if (!MOP.isReg() || !MOP.readsReg())
      continue;
    addReg(MOP.getReg());
  }
}
```

</pre>
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