<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/60233>60233</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AArch64] Compile `x != 0` to `umin x, 1` when CSSC is available
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Kmeakin
      </td>
    </tr>
</table>

<pre>
    # Input
```llvm
define i32 @src(i32 %0) {
  %2 = icmp ne i32 %0, 0
  %3 = zext i1 %2 to i32
  ret i32 %3
}

define i32 @tgt(i32 %0) {
  %2 = tail call i32 @llvm.umin.i32(i32 %0, i32 1)
  ret i32 %2
}
```

# Output
```asm
src:
  cmp w0, #0
  cset w0, ne
 ret
tgt:
  umin w0, w0, #1
 ret
```

[Proof](https://alive2.llvm.org/ce/z/DTLxub)
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyMk9-OmzwQxZ9muLE2ssf8CRdcZIOQPn2VWmn7AgYmwa2BCJsk3aev7EA23eaiUqQkw5njMz_Gylp9HIgKSF4hKSM1u26civ97Uj_1ENVj-6sAlOy_4TQ74CXwHaT89jHm3N9KLR30QExLZBBzOzWA2_AHEw6YM8heb0LmS8hAlkw3_YmtTUG3Z_xBJYPqna6OaXFrc6NXr5qJ3Nosl2RZufx4ksod3T-kckob1ihj1jY_5Gbu9bDxRz8a7INEAOZPEuHnRCu0x4Ae7NfZ_U1W2QWsRyl3q78ndgknA8o7q8aSW8oDLcWJFks_9YeBn2OR3n3E55bnUZPXb9M4HiApAbedcyfrfbECrJTRZ8JNIDVOR8CqIcDqHbAqv3-5zjVgHrWFbHOZq4gKkWZxnG55LqKuSLls-SEXIqEsadq0TuJDncfxNiVOrZKRLpCj5AKl4FxIsVGE2zZOGpWqrG3aDGJOvdLmHiDS1s5UpByljIyqydiw3ogDXVh4CIh-26fC97zU89H6V62tsx8uTjsT7sVuNzVdGkNSsv3Yn7QhBim_MkDhV8aj8qsJKQ98rx6s8MVLRwPbv73tmbZMnZU2qjYUzZMp_iR41K6b600z9oBVuFa3r5fTNP6gxgFWIbYFrMJYvwMAAP__4QAAIg">