<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/60077>60077</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Incorrect integer disassembler tests containing 0x3800 aka 0.5
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            test-suite,
            backend:AMDGPU
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Sisyph
      </td>
    </tr>
</table>

<pre>
    @dpreobra @mbrkusanin @arsenm @rampitec @jayfoad  

Example test line:
0x05,0x00,0x4d,0xd6,0x7d,0xe0,0xf5,0x01

What this line would decode to in sp3:
v_max3_i16 v5, m0, 0.5, m0

As of fc4c1a86f35f3, the test check was:
v_max3_i16 v5, m0, 0x3800, m0           ; encoding: [0x05,0x00,0x4d,0xd6,0x7d,0xfe,0xf5,0x01,0x00,0x38,0x00,0x00]

After 7e1963b1917f533d4283da43a8d016e2138c9cf6 the check is:
v_max3_i16 v5, m0, 0x3800, m0

What should we do?
1. delete the tests
2. modify the input so it is in the form with a literal
3. update the checks so the output has the literal
4. change the compiler behavior

I'm not in favor of 3 because it is not round trippable, and so can cause issues with tooling.

The spec says:
"Float constants work with single, double and 16bit float instructions, and when used in non-float
instructions, the data is not converted (remains a float)."

This compiler behavior (not allowing fp inline constants in integer instructions) is on purpose according to the following comment, so I'm not in favor of 4
https://github.com/llvm/llvm-project/blob/cd8cac438d0f175aae88a9f412cb69317be7ffc6/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp#L3789


Affected tests:

$grep 0x3800 | grep -v encoding

gfx11_dasm_vop3.txt:# GFX11: v_min3_i16 v5, 0x3800, m0, 0x3800 op_sel:[0,1,0,0]
gfx11_dasm_vop3.txt:# GFX11: v_min3_u16 v5, m0, 0x3800, m0
gfx11_dasm_vop3.txt:# GFX11: v_min3_u16 v5, 0x3800, m0, 0x3800 op_sel:[0,1,0,0]
gfx11_dasm_vop3.txt:# GFX11: v_min_i16 v5, m0, 0x3800
gfx11_dasm_vop3.txt:# GFX11: v_min_i16 v5, 0x3800, m0
gfx11_dasm_vop3.txt:# GFX11: v_min_u16 v5, m0, 0x3800
gfx11_dasm_vop3.txt:# GFX11: v_min_u16 v5, 0x3800, m0
gfx11_dasm_vop3.txt:# GFX11: v_mul_lo_u16 v5, m0, 0x3800
gfx11_dasm_vop3.txt:# GFX11: v_mul_lo_u16 v5, 0x3800, m0
gfx11_dasm_vop3.txt:# GFX11: v_or_b16 v5, m0, 0x3800
gfx11_dasm_vop3.txt:# GFX11: v_or_b16 v5, 0x3800, m0
gfx11_dasm_vop3.txt:# GFX11: v_sub_nc_i16 v5, m0, 0x3800
gfx11_dasm_vop3.txt:# GFX11: v_sub_nc_i16 v5, 0x3800, m0 op_sel:[1,0,0]
gfx11_dasm_vop3.txt:# GFX11: v_sub_nc_u16 v5, m0, 0x3800
gfx11_dasm_vop3.txt:# GFX11: v_sub_nc_u16 v5, 0x3800, m0 op_sel:[1,0,0]
gfx11_dasm_vop3.txt:# GFX11: v_xor_b16 v5, m0, 0x3800
gfx11_dasm_vop3.txt:# GFX11: v_xor_b16 v5, 0x3800, m0
gfx11_dasm_vop3p.txt:# GFX11: v_pk_add_i16 v5, m0, 0x3800
gfx11_dasm_vop3p.txt:# GFX11: v_pk_add_i16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
gfx11_dasm_vop3p.txt:# GFX11: v_pk_add_u16 v5, m0, 0x3800
gfx11_dasm_vop3p.txt:# GFX11: v_pk_add_u16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
gfx11_dasm_vop3p.txt:# GFX11: v_pk_ashrrev_i16 v5, m0, 0x3800
gfx11_dasm_vop3p.txt:# GFX11: v_pk_ashrrev_i16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
gfx11_dasm_vop3p.txt:# GFX11: v_pk_lshlrev_b16 v5, m0, 0x3800
gfx11_dasm_vop3p.txt:# GFX11: v_pk_lshlrev_b16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
gfx11_dasm_vop3p.txt:# GFX11: v_pk_lshrrev_b16 v5, m0, 0x3800
gfx11_dasm_vop3p.txt:# GFX11: v_pk_lshrrev_b16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
gfx11_dasm_vop3p.txt:# GFX11: v_pk_mad_i16 v5, m0, 0x3800, m0
gfx11_dasm_vop3p.txt:# GFX11: v_pk_mad_i16 v5, 0x3800, m0, 0x3800 op_sel:[1,0,0] op_sel_hi:[0,1,1]
gfx11_dasm_vop3p.txt:# GFX11: v_pk_mad_u16 v5, m0, 0x3800, m0
gfx11_dasm_vop3p.txt:# GFX11: v_pk_mad_u16 v5, 0x3800, m0, 0x3800 op_sel:[1,0,0] op_sel_hi:[0,1,1]
gfx11_dasm_vop3p.txt:# GFX11: v_pk_max_i16 v5, m0, 0x3800
gfx11_dasm_vop3p.txt:# GFX11: v_pk_max_i16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
gfx11_dasm_vop3p.txt:# GFX11: v_pk_max_u16 v5, m0, 0x3800
gfx11_dasm_vop3p.txt:# GFX11: v_pk_max_u16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
gfx11_dasm_vop3p.txt:# GFX11: v_pk_min_i16 v5, m0, 0x3800
gfx11_dasm_vop3p.txt:# GFX11: v_pk_min_i16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
gfx11_dasm_vop3p.txt:# GFX11: v_pk_min_u16 v5, m0, 0x3800
gfx11_dasm_vop3p.txt:# GFX11: v_pk_min_u16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
gfx11_dasm_vop3p.txt:# GFX11: v_pk_mul_lo_u16 v5, m0, 0x3800
gfx11_dasm_vop3p.txt:# GFX11: v_pk_mul_lo_u16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
gfx11_dasm_vop3p.txt:# GFX11: v_pk_sub_i16 v5, m0, 0x3800
gfx11_dasm_vop3p.txt:# GFX11: v_pk_sub_i16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
gfx11_dasm_vop3p.txt:# GFX11: v_pk_sub_u16 v5, m0, 0x3800
gfx11_dasm_vop3p.txt:# GFX11: v_pk_sub_u16 v5, 0x3800, m0 op_sel:[1,1] op_sel_hi:[0,0]
gfx11_dasm_vopcx.txt:# GFX11: v_cmpx_eq_i16_e32 0x3800, v2
gfx11_dasm_vopcx.txt:# GFX11: v_cmpx_eq_u16_e32 0x3800, v2
gfx11_dasm_vopcx.txt:# GFX11: v_cmpx_ge_i16_e32 0x3800, v2
gfx11_dasm_vopcx.txt:# GFX11: v_cmpx_ge_u16_e32 0x3800, v2
gfx11_dasm_vopcx.txt:# GFX11: v_cmpx_gt_i16_e32 0x3800, v2
gfx11_dasm_vopcx.txt:# GFX11: v_cmpx_gt_u16_e32 0x3800, v2
gfx11_dasm_vopcx.txt:# GFX11: v_cmpx_le_i16_e32 0x3800, v2
gfx11_dasm_vopcx.txt:# GFX11: v_cmpx_le_u16_e32 0x3800, v2
gfx11_dasm_vopcx.txt:# GFX11: v_cmpx_lt_i16_e32 0x3800, v2
gfx11_dasm_vopcx.txt:# GFX11: v_cmpx_lt_u16_e32 0x3800, v2
gfx11_dasm_vopcx.txt:# GFX11: v_cmpx_ne_i16_e32 0x3800, v2
gfx11_dasm_vopcx.txt:# GFX11: v_cmpx_ne_u16_e32 0x3800, v2
gfx11_dasm_vop3_from_vop1.txt:# GFX11: v_cvt_f16_i16_e64 v5, 0x3800 mul:2
gfx11_dasm_vop3_from_vop1.txt:# GFX11: v_cvt_f16_u16_e64 v5, 0x3800 mul:2
gfx11_dasm_vop3_from_vop1.txt:# GFX11: v_cvt_i32_i16_e64 v5, 0x3800
gfx11_dasm_vop3_from_vop1.txt:# GFX11: v_cvt_u32_u16_e64 v5, 0x3800
gfx11_dasm_vop3_from_vop1.txt:# GFX11: v_not_b16_e64 v5, 0x3800
gfx11_dasm_vopc.txt:# W32: v_cmp_eq_i16_e32 vcc_lo, 0x3800, v2
gfx11_dasm_vopc.txt:# W32: v_cmp_eq_u16_e32 vcc_lo, 0x3800, v2
gfx11_dasm_vopc.txt:# W32: v_cmp_ge_i16_e32 vcc_lo, 0x3800, v2
gfx11_dasm_vopc.txt:# W32: v_cmp_ge_u16_e32 vcc_lo, 0x3800, v2
gfx11_dasm_vopc.txt:# W32: v_cmp_gt_i16_e32 vcc_lo, 0x3800, v2
gfx11_dasm_vopc.txt:# W32: v_cmp_gt_u16_e32 vcc_lo, 0x3800, v2
gfx11_dasm_vopc.txt:# W32: v_cmp_le_i16_e32 vcc_lo, 0x3800, v2
gfx11_dasm_vopc.txt:# W32: v_cmp_le_u16_e32 vcc_lo, 0x3800, v2
gfx11_dasm_vopc.txt:# W32: v_cmp_lt_i16_e32 vcc_lo, 0x3800, v2
gfx11_dasm_vopc.txt:# W32: v_cmp_lt_u16_e32 vcc_lo, 0x3800, v2
gfx11_dasm_vopc.txt:# W32: v_cmp_ne_i16_e32 vcc_lo, 0x3800, v2
gfx11_dasm_vopc.txt:# W32: v_cmp_ne_u16_e32 vcc_lo, 0x3800, v2

</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzEWVFv4yoW_jXkBU1kg-PYD3noTDdXlXalle5d3X2zMBzb3GLwAk7Tf7_CTlpn2s5NUk-mUmtj4Dvf9x04ooI5J2sNsEGrr2h1v2C9b4zd_C7dc9csSiOeNyiJRGfBlJZhlERtaR97x7TUocWsA92GN8vaTnrg4f0v9lwZJjBG0T2K7sa__9iztlOAPTiPldSA6KEn2kcrRL5F-ygaHokYHiIdHuuxBWNfdRgZT6H_bJjHvpFuwMVPplcCC-BGAPYGS41dR1_C7YqW7Wkh4xTvAhpuAzSOlsfGBPnOYVPhiic8Zlla0VVFwyDfHHTwBvgjfmLub9H3NBvk4TbCrz-IfsWguRFS14jeYbT6epYbFXznxmQCzaatKEKr-xNJlQeL1xDnKS3jPF5XK0pFQjIqWEJZJqI4BRLTjOe8Sgepo0p5kcg3-XHNkJYnwMIguh174iUWoMDDi6Vu7CBL3Bohq-ehQ-qu99gZLD2WLiQ0fK2MbfGT9A1mWEkPlqlxMl3ivhPsgDqwd2F2aJneB6yGuaF5Mi9ZYt4wXR_mmbaTCiwuoWE7aexU0gMi6xZr4wOZiu2MDQuF4hI46x0ciIZ-a3otsLey61ipQt4w0yLQ4Uzjw2jnenCjFm-MkrpeTqP90QB2HXDs2PNrFhAhW2WYx9xo55n2Dj8Z-zjCOKnrMZowfalgCBqnpfS4GiZJ7bztuZdGuyOppwY07h2IoEob_WUYOkb7fnywSDDPjjq50TuwHgRGJLPQMqkdZmMwRPIlIuRUknRvLQ5zAxhTyjxJXeOqw1IPu_pVpNRYag812O9E5IGL0bjrbWccYMa5sWFrhSowrpgjLjdtC9oHIc7g97OZjEwb77vBdLJFZFtL3_TlkpsWka1Su-PjS2fNX8A9IttSmRKRLRcZZzyhmYiqeL1iDLKM5VUSE16mOY3XJayriqcTHBnm_cFsDQHn7l_3v_37P4hsf394CDofdGWWvOsQof-k6yyf2nnc2xXwkIJxJ9GTTkSS2kJ32KUYrb_hof1l91qCJsPrah_HhWCuLXamo0u_94MJFP-2_W8ch2q1K1qpp2XgpAC8tLHpCgcqzF59Dd-HcjX8HkvT-cH6v60512D9dOIf1cprQa6X_ZGD14Jcy6RXhTIzkPke50o-xhblZ7mcYFzJw_Vlofnnl8sbnJMTyHRhX7moDwE-ncA3OHMT3c-R2v1lue3eR-keCybEJck9F-iHpsVodX_4WDTytZx9aOSPo16Q8nOBbkbfNdbCbqYMvAG7lQzlGhUiX7CsLwG7oQw7pwz7a2S07MMtfU2FOIU742QyrYvvSTrKvYLHxaetc-F-paz9PNv_FOh2i20_TwE-BboZ_cuOwucC3ZL-PO5_eIb-qfQvPnRfgHUrEeHAOMsSOgW6Jf1ZEnAKNCt9vn8_Km-7fQH_C64VQMkk6I5cg9PPgVPDPHxqmImPn4mPn4ePmskfNZM_aiZ_1Ez-6Jn80ef7Q4vKmuEt_gBw54sqTkdiaXKyx3Hbh639OeD-ZwBLSt5lfDVgT8m7TK8C1MaHfw7OAuMTiD8pecnytPjtOC-UOa29HyybH6D186FNCuE8aHNy87Ny83NyU7P6pmb1Tc3qm5rVNz2rb_o83xZiQ0VOc7aATZyuaZalqyRfNBtIUshzLnKRZCtKsirjIqsYL9eEJnHMFnJDIkKjOE7jlORRvkwhKasVrzLKIa0iQEkELZNqqdSuXRpbL4Z7uU0aRev1QrESlBsuygnx4PwX10sPiBBEviFCSsYfQQtE7473NgSt7hd2M9wOlX3tUBIp6bx7xffSK9g8aG6sBe5frrWEdMw5aEsFdrzLwdxoz6SWuj5Wa_bIcLRcLXqrNhffUY03johsB3H_DwAA__96bGQT">