<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/60043>60043</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Add slow LEA schedule information for Intel CPUs
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          phoebewang
      </td>
    </tr>
</table>

<pre>
    According to Intel SOM, different microarchitectures have different limitations in the use of LEA instructions, aka slow LEA in some cases. But none of current Intel schedule model describes it. It would be helpful if we model them correctly.
There are 3 major different slow cases:

- LEA with three source operands: base, index, and offset. This case exists in Core microarchitectures since Sandybridge till Icelake;
- LEA with valid index. This case exists in Atom microarchitectures Silvermont, Goldmont and Goldmont Plus;
- LEAs without a scaled index and with only two sources among base, index, and displacement. This case exists in Gracemont;

There are also other limitations with some microarchitecture, e.g., base/index registers, partial register smaller than 4 bytes, index is on the critical path etc. I think it's hard to model such granularity in schedule model.
</pre>
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