<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/59837>59837</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [ARM][as] [MC] llvm not support ADC.W/SBC.W/ADCS.W/SBCS.W/ORNS.W instruction when Operand2 is constant
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Neilzhangtianhao
      </td>
    </tr>
</table>

<pre>
    The asm code is
```
     .thumb ; .syntax unified

    ADC.W R3,R1,#0x55555555
    SBC.W R2,R3,#0xAAAAAAAA
 ADCS.W R3,R1,#0xFFFFFFFF
    SBCS.W R3,R1,#0xFFFFFFFF
    ORNS.W R3,R1,#0xFFFFFFFF
```

My compiling ommands is 
`clang -c -mthumb -mcpu=cortex-m4 --target=arm-none-eabi -x assembler-with-cpp adc_tmp.s`

provoke this error

```
./adc_tmp.s:6:5: error: invalid instruction, any one of the following would fix this:
    ADC.W R3,R1,#0x55555555
    ^
./adc_tmp.s:6:17: note: invalid operand for instruction
    ADC.W R3,R1,#0x55555555
 ^
./adc_tmp.s:6:17: note: operand must be a register in range [r0, r12] or r14
    ADC.W R3,R1,#0x55555555
                ^
./adc_tmp.s:7:5: error: invalid instruction, any one of the following would fix this:
 SBC.W R2,R3,#0xAAAAAAAA
    ^
./adc_tmp.s:7:17: note: invalid operand for instruction
    SBC.W R2,R3,#0xAAAAAAAA
 ^
./adc_tmp.s:7:17: note: operand must be a register in range [r0, r12] or r14
    SBC.W R2,R3,#0xAAAAAAAA
                ^
./adc_tmp.s:8:5: error: invalid instruction, any one of the following would fix this:
 ADCS.W R3,R1,#0xFFFFFFFF
    ^
./adc_tmp.s:8:18: note: invalid operand for instruction
    ADCS.W R3,R1,#0xFFFFFFFF
 ^
./adc_tmp.s:8:18: note: operand must be a register in range [r0, r12] or r14
    ADCS.W R3,R1,#0xFFFFFFFF
                 ^
./adc_tmp.s:9:5: error: invalid instruction, any one of the following would fix this:
 SBCS.W R3,R1,#0xFFFFFFFF
    ^
./adc_tmp.s:9:18: note: invalid operand for instruction
    SBCS.W R3,R1,#0xFFFFFFFF
 ^
./adc_tmp.s:9:18: note: operand must be a register in range [r0, r12] or r14
    SBCS.W R3,R1,#0xFFFFFFFF
                 ^
```

clang version

```
clang version 16.0.0 (https://github.com/llvm/llvm-project.git 7f017376875815c5a5dece807dcb397e267a97aa)
Target: x86_64-unknown-linux-gnu
Thread model: posix
InstalledDir: /home/zth/llvm/./install_arm/build_install/bin
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/11
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/7
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/7.5.0
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/8
Selected GCC installation: /usr/lib/gcc/x86_64-linux-gnu/11
Candidate multilib: .;@m64
Candidate multilib: 32;@m32
Candidate multilib: x32;@mx32
Selected multilib: .;@m64
```

I use gcc to compile it, it's ok

`arm-none-eabi-gcc -c -mthumb -mcpu=cortex-m4 -x assembler-with-cpp ./adc_tmp.s`


ADD, ADC, SUB, SBC, and RSB instruction declaration in ARM
https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-instruction-set/general-data-processing-instructions/add--adc--sub--sbc--and-rsb?lang=en

</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJy0V11zmzoT_jXyzY4YkIzBF77wx8s7vWg7k_TMucwItAadguSRROL0158RkA_npKndJhoPGHi0--w-7EoI51StEVck3ZB0NxO9b4xdfUHV_miErr0SuhFmVhp5v_rWIAjXQWUkgnIk3pF4TRbx9BsuIYzIN31XAuEbiNy99uIIvVZ7hXKa8whd77bR33DFCdteJYRtCePxMZ3GE-x6M8BYgPEH2HoaE2y9217_11YxjRNbZ-G-Xn35Je5F8OPx8z1UpjuoVukaTNcJLR0oB49TqlboGmgFtBsTRbvq0BO-q4z1eKTdHCj1wtboCd8J21FtNFIUpQJ6BOEcdmWLlt4p39DqcAAhqxvfHSL3gsrBmlvzHcE3ygFaa-zzpy_YR4QVT4b4ekH4OiV8PU3ka1D6VrRKgtLO277yymjCtiD0PRiNYPbgG4S9aVtzF4K_M30rYa-OAwHCLxeepP_7ObkkC6S08ficnDmgFVrC3tgTohe5vsDvg7-udx5KBAEWa-U8Bvdgha4RSLqxcUiVTRhJd2As2GR-cTaej58yzD5MtnOq8FfMflOzc1xf4Pc9NDszG2dpln-YZud2xTepJfnvFtqvfV_g-J0q7ax8nKfb8iNr7c90W_6-bmf5vsDxO1XbH-j26jo9LsO3aN1j9K-iT3CQLKI4ioGwvPH-MCjGCsKKWvmmL6PKdIQVbXv7cKIHa_7Byke18pDt4yTj2SLP0jxJq1SkEivM40xWJV9myBaZWGZCELYcfX-bdgFrOOaLm8Wc9vq7Nneatkr3R1rrfsI1FoWEzkhsA_pgnDqOjz5p50Xbotyp4Q0lrGhMh4QVP3zzxDXIqEbojbDhTtmrVt5M98K1mrJUmF5LqISWSgqP8P_tFiaYGN6k0UvvbDCvypCdqiKsmGJ44s6KJHl_m9kHmIzSKH5_s_lo8hpbrDzKd8nk9pFZ17dehVl8DRHhGzKPu8X8LRRnE4yzt2DHR9zxAfgYwltOXy3DT9A7hLqqwJtp44ygfOgF4Zg5MN9fVOfJlpiGqW9vpl_dM5_2rVNO43G92wUW6902nK7_2gynzXZs6BKurjfPGyhIrFphB-FCY1tffR7tnDYKibfYhpYYCdtN_UKaqu9Q-1F0VshexWnKAkPCCt8gfYiG02ceqUMfXgnUaEVLpfAitJsKnVO6fo50Q7CSUiErSl1fUurKilKhJbWuJLwITY7wHU41PpMrLpd8KWa4ShYZy5fLBU9mzSrPcj5PWZLyMkuW6Z4zlnCZLZdpKhJRlTO1YjHjcRKn8YLFPIlygftUsHiRL0qe8yWZx9gJ1Uah80TG1jPlXI-rdJnzbNaKEls3fI8ypvEOhoeEhVVhZldDSy372pF53Crn3ZMVr3w7fMiGxKc7km6EC0sJSTeft-FPQIZFCVx_OBjrx203YcWwlSOsGDcH443xz_QR-FzluwY1fB2XNBa-6yoTKlb7WW_b1WWLQui5IbwgzxD-vwEAAP__ExeHhQ">