<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/59837>59837</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[ARM][as] [MC] llvm not support ADC.W/SBC.W/ADCS.W/SBCS.W/ORNS.W instruction when Operand2 is constant
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
Neilzhangtianhao
</td>
</tr>
</table>
<pre>
The asm code is
```
.thumb ; .syntax unified
ADC.W R3,R1,#0x55555555
SBC.W R2,R3,#0xAAAAAAAA
ADCS.W R3,R1,#0xFFFFFFFF
SBCS.W R3,R1,#0xFFFFFFFF
ORNS.W R3,R1,#0xFFFFFFFF
```
My compiling ommands is
`clang -c -mthumb -mcpu=cortex-m4 --target=arm-none-eabi -x assembler-with-cpp adc_tmp.s`
provoke this error
```
./adc_tmp.s:6:5: error: invalid instruction, any one of the following would fix this:
ADC.W R3,R1,#0x55555555
^
./adc_tmp.s:6:17: note: invalid operand for instruction
ADC.W R3,R1,#0x55555555
^
./adc_tmp.s:6:17: note: operand must be a register in range [r0, r12] or r14
ADC.W R3,R1,#0x55555555
^
./adc_tmp.s:7:5: error: invalid instruction, any one of the following would fix this:
SBC.W R2,R3,#0xAAAAAAAA
^
./adc_tmp.s:7:17: note: invalid operand for instruction
SBC.W R2,R3,#0xAAAAAAAA
^
./adc_tmp.s:7:17: note: operand must be a register in range [r0, r12] or r14
SBC.W R2,R3,#0xAAAAAAAA
^
./adc_tmp.s:8:5: error: invalid instruction, any one of the following would fix this:
ADCS.W R3,R1,#0xFFFFFFFF
^
./adc_tmp.s:8:18: note: invalid operand for instruction
ADCS.W R3,R1,#0xFFFFFFFF
^
./adc_tmp.s:8:18: note: operand must be a register in range [r0, r12] or r14
ADCS.W R3,R1,#0xFFFFFFFF
^
./adc_tmp.s:9:5: error: invalid instruction, any one of the following would fix this:
SBCS.W R3,R1,#0xFFFFFFFF
^
./adc_tmp.s:9:18: note: invalid operand for instruction
SBCS.W R3,R1,#0xFFFFFFFF
^
./adc_tmp.s:9:18: note: operand must be a register in range [r0, r12] or r14
SBCS.W R3,R1,#0xFFFFFFFF
^
```
clang version
```
clang version 16.0.0 (https://github.com/llvm/llvm-project.git 7f017376875815c5a5dece807dcb397e267a97aa)
Target: x86_64-unknown-linux-gnu
Thread model: posix
InstalledDir: /home/zth/llvm/./install_arm/build_install/bin
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/11
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/7
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/7.5.0
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/8
Selected GCC installation: /usr/lib/gcc/x86_64-linux-gnu/11
Candidate multilib: .;@m64
Candidate multilib: 32;@m32
Candidate multilib: x32;@mx32
Selected multilib: .;@m64
```
I use gcc to compile it, it's ok
`arm-none-eabi-gcc -c -mthumb -mcpu=cortex-m4 -x assembler-with-cpp ./adc_tmp.s`
ADD, ADC, SUB, SBC, and RSB instruction declaration in ARM
https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-instruction-set/general-data-processing-instructions/add--adc--sub--sbc--and-rsb?lang=en
</pre>
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