<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/59647>59647</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AArch64] `srem` with vector of -1's crashes backend when targeting Cortex A710
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          HazyFish
      </td>
    </tr>
</table>

<pre>
    ## Description

The following code containing `srem` with the second operand being a vector of -1's crashes AArch64 backend with assertion `N1.getValueType() == N2.getValueType() && N1.getValueType() == VT && "Binary operator types must match!"` failed when targeting `cortex-a710`.

The code can compile successfully when CPU is not specified.

## Minimal Reproduction

https://godbolt.org/z/xxqb49rhW

### Code

```ll
define void @f(ptr %0, <4 x i16> %1) {
BB:
  %B = srem <4 x i16> %1, <i16 -1, i16 -1, i16 -1, i16 -1>
  store <4 x i16> %B, ptr %0
  ret void
}
```

### Stack Trace

```console
llc: /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:6159: llvm::SDValue llvm::SelectionDAG::getNode(unsigned int, const llvm::SDLoc &, llvm::EVT, llvm::SDValue, llvm::SDValue, const llvm::SDNodeFlags): Assertion `N1.getValueType() == N2.getValueType() && N1.getValueType() == VT && "Binary operator types must match!"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: ./llvm-project-latest/build-debug/bin/llc -mtriple=aarch64 -mcpu=cortex-a710 ./crash-reports/dagisel-aarch64/cortex-a710/1.ll
1.      Running pass 'Function Pass Manager' on module './crash-reports/dagisel-aarch64/cortex-a710/1.ll'.
2.      Running pass 'AArch64 Instruction Selection' on function '@f'
 #0 0x00007f998056bf2a llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/Support/Unix/Signals.inc:567:11
 #1 0x00007f998056c0db PrintStackTraceSignalHandler(void*) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/Support/Unix/Signals.inc:641:1
 #2 0x00007f998056a756 llvm::sys::RunSignalHandlers() /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/Support/Signals.cpp:104:5
 #3 0x00007f998056c805 SignalHandler(int) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/Support/Unix/Signals.inc:412:1
 #4 0x00007f997ed00980 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x12980)
 #5 0x00007f997dffce87 raise /build/glibc-CVJwZb/glibc-2.27/signal/../sysdeps/unix/sysv/linux/raise.c:51:0
 #6 0x00007f997dffe7f1 abort /build/glibc-CVJwZb/glibc-2.27/stdlib/abort.c:81:0
 #7 0x00007f997dfee3fa __assert_fail_base /build/glibc-CVJwZb/glibc-2.27/assert/assert.c:89:0
 #8 0x00007f997dfee472 (/lib/x86_64-linux-gnu/libc.so.6+0x30472)
 #9 0x00007f9980d03d29 llvm::SelectionDAG::getNode(unsigned int, llvm::SDLoc const&, llvm::EVT, llvm::SDValue, llvm::SDValue, llvm::SDNodeFlags) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:6162:9
#10 0x00007f9980ce2300 llvm::SelectionDAG::getNode(unsigned int, llvm::SDLoc const&, llvm::EVT, llvm::SDValue, llvm::SDValue) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:6079:10
#11 0x00007f99930ffca7 llvm::AArch64TargetLowering::LowerFixedLengthVectorIntDivideToSVE(llvm::SDValue, llvm::SelectionDAG&) const /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22816:17
#12 0x00007f99930ce104 llvm::AArch64TargetLowering::LowerDIV(llvm::SDValue, llvm::SelectionDAG&) const /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:12772:12
#13 0x00007f99930bd174 llvm::AArch64TargetLowering::LowerOperation(llvm::SDValue, llvm::SelectionDAG&) const /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:5897:12
#14 0x00007f9980ba8d77 (anonymous namespace)::VectorLegalizer::LowerOperationWrapper(llvm::SDNode*, llvm::SmallVectorImpl<llvm::SDValue>&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:514:21
#15 0x00007f9980ba7dbb (anonymous namespace)::VectorLegalizer::LegalizeOp(llvm::SDValue) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:493:9
#16 0x00007f9980ba3873 (anonymous namespace)::VectorLegalizer::LegalizeOp(llvm::SDValue) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:253:19
#17 0x00007f9980ba3873 (anonymous namespace)::VectorLegalizer::LegalizeOp(llvm::SDValue) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:253:19
#18 0x00007f9980baa0f9 (anonymous namespace)::VectorLegalizer::RecursivelyLegalizeResults(llvm::SDValue, llvm::MutableArrayRef<llvm::SDValue>) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:237:18
#19 0x00007f9980ba7f44 (anonymous namespace)::VectorLegalizer::LegalizeOp(llvm::SDValue) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:507:10
#20 0x00007f9980ba3583 (anonymous namespace)::VectorLegalizer::Run() /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:206:5
#21 0x00007f9980ba336b llvm::SelectionDAG::LegalizeVectors() /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:1707:33
#22 0x00007f9980d6b6aa llvm::SelectionDAGISel::CodeGenAndEmitDAG() /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:847:13
#23 0x00007f9980d6abbd llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Instruction, true, false, void>, false, true>, llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Instruction, true, false, void>, false, true>, bool&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:701:1
#24 0x00007f9980d6a64d llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1641:11
#25 0x00007f9980d67b27 llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:480:3
#26 0x00007f999304c755 (anonymous namespace)::AArch64DAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:58:5
#27 0x00007f9983d801d5 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/MachineFunctionPass.cpp:91:8
#28 0x00007f9982ec8676 llvm::FPPassManager::runOnFunction(llvm::Function&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/IR/LegacyPassManager.cpp:1430:23
#29 0x00007f9982ecd4a2 llvm::FPPassManager::runOnModule(llvm::Module&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/IR/LegacyPassManager.cpp:1476:16
#30 0x00007f9982ec8f49 (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/IR/LegacyPassManager.cpp:1545:23
#31 0x00007f9982ec8abd llvm::legacy::PassManagerImpl::run(llvm::Module&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/IR/LegacyPassManager.cpp:535:16
#32 0x00007f9982ecd781 llvm::legacy::PassManager::run(llvm::Module&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/IR/LegacyPassManager.cpp:1672:3
#33 0x0000000000419b16 compileModule(char**, llvm::LLVMContext&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/tools/llc/llc.cpp:737:41
#34 0x0000000000417eaa main /home/henry/aflplusplus-isel/llvm-project-latest/llvm/tools/llc/llc.cpp:418:13
#35 0x00007f997dfdfc87 __libc_start_main /build/glibc-CVJwZb/glibc-2.27/csu/../csu/libc-start.c:344:0
#36 0x00000000004176aa _start (./llvm-project-latest/build-debug/bin/llc+0x4176aa)
```

## Cause

In method `AArch64TargetLowering::LowerFixedLengthVectorIntDivideToSVE`, `ISD::SUB` node is being created in Line 22816 with 2 operands of different types (**v4i16** and **nxv8i16**), causing the assertion error.

https://github.com/llvm/llvm-project/blob/a40ef656d812143d24c810c65ebf6b24646837f0/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L22808-L22819
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzkWl9z5CYS_zT4hZophCQkPfhh7PEkvrKzLttxqu5lCiE0w4UBHSCvJ5_-CqT5I6293t1s1k5uy2tLSGr69-umaaCptWKlOD8F6RlI5ye0dWttTn-mf2wXwq5PSl1tTwGOAY7hnFtmROOEVgDNAZp1v-_XHNZaSv1RqBVkuuKQaeWoUP4eEGQN3wCC4Efh1tCtObScaVVB3XBDVQVL7l-k8JEzpw3UNZxEAGcWMkPtmls4mxm2JgksKfudq6oTRK3lxuviu_glmq64e6Cy5ffbhgOcA1xAEM9BPIe_4GcfYgIwgZ_98uF-9xrA-Ewoarad1l5Pt224hZvWOrihjq0BjgDGHmhNheQV_LjmCjpqVtz1TDBtHH-a0CxCgKDpmMWOO6og05tGSA5tyxi3tm6l3Hbizm9-hcJCpR20DWeiFrwayOltdS2U2FAJb3ljdNWysdHWzjUWxDOAFwAvVroqtXRTbVYAL_4AePH09N8yKcz6t09le_HnuuKDJwR1P1J2DRWvheLwUYsKggTVAOeNMxDgFAF8DkF8nsAnKCIC4gvfGgXWs7Pu67Mzr1q4hP7pmTcI9H707JdBnohI8Jtz-Jmr-GIn1Tpt-KfSzvzLe037dw13AUmPNZuPQD_P0Z2j7Hd4byh7niqmldWyfyYlA_EMArxY6w33f7gyW4AXtJaNbK3_PxGWS4AXUj5uJo3R_-HMTSR13Lq-1f8RJcALb5-fuAJ4ccclD9afz34a3U5Z04B4RqK08H0HAfEMxLO7eRgPxy3HUkLLirtfvBPgvFUhhFRQKOfZ87jcQNqVZt04Oj9qvni4Hzb0vb7Y-Klcr8BC0pUFOCCYvdOQgLM-JPQj9ebqYnZ3AW1bboSDFJbtChreaOOg03A0NIVbt-WU6c2RjY8cAOCFsLblFuAF9NFUKCbbiodAGwJoCJvOu2HffeeYVbtp9qPMx6LixuiVoRtIzardcOW8EnD6osOVrZDVpOJl64NGKVR4k8HJxhnRSA7iOaVd4J5sWNOCeH4U_4LgoN-kg-4BVHTlfXzSf-ffOIqYeBFNd_El8grftirMMQ21FgKcLVoVnBTe-IZrquiKG8--VnCjq1Zy_9Y3d-w_DZ3j5zrfTVKXyjrTBVy4Hza9EvVOQYCzLipmfYwBOEYQPSGEUFYXRY5SUtaYHrm73dru4sYI5YINu9iC88NLhn5causMp5t-wIVBWXy3wHLXNp4zgBe_KvHkG8RKUWmnQvkAlpIMxLMoOqCKRqgYqko4gtDJ-JmqSnp75SHW4tkP1Jskkdf7oDYeqU2zlDxnjNtWDbS3-1DyvfXeKdwF7Qglnu6DwvGY5xylcEzsj3WGJMJDUpMjHTNeIVTkCC6XhofJeGkcDOz10p9ysiTJRArVPk1Wqu0eNG5tOK2mVk8RwGfoKcJFjvwEsO8mPe6mqmvG8wwaKqwf_l3Y8oFVipJNzh_-9fHf5f4WT3EG8MIGHAAvpj5Y2K2teOPDRNvBtFv7GLRRrb8NoqfB_b0XoYMmZKQJz-oI0lIHpF-mias6NsJXoZN81Ek27ITzuKZwuezy46WfeJYl_XLs3Xf7i67LYthlPu4yyfAX2I55q5FgtRglGR5YrRg4cIXiChffmIGMc4-QOfz5BOSl1OONsjbiR1exzzqj4fzBOI4Rek8EvhFPKCtCvDwQdTwlFTGqa0azI4X7ifw-LNyu9EduhFp1j8LdQjzx6oqrlVs_hBXrpXJz8Sgqfq_vHi4G8_HzjAyUJp6ZLrf9Xvx0qgO86KEcri7vuNxB6gnCOPern1mUHRjCQ4YYj1DyFQzNLx_-bixEOMvCbIUPLMRDFsoqyr6GhQ9hVRCSv78XF2leZCMqkkFsKWleZZkP-FRptd3o1kJFN9w2IR8tOlDd4LjiKyrFH9w8x8xvhjZNyEzGsTWkfwOKNlTKfrxtGgni8085jS968v7yQLND1Sn0odmlZWnk0zIcHZhLR8xlVVl-G3P97YfmeX96Q9RJEQ-nIjICHedZ_E8DjVMPOjpCnf1fos5HqCmqi29CfctZa6x45HK7e3LLbSv9Av21AHrdOlpKPjOGbm95_WJ0eEvm4hBU8wNzxTg01EnyT_OXFGXD7Auj8ShJ828bJbet-s6L7a-3KSKHVbgHF43BxaT8bA4-lPy9dw--GlCUBXvF8QHScCekIiWh9AVIPpfoWvuOZ6q62AgX-vwxwMbq9LjyJLjhEax4BIuWZfUqrK71jFrBzqRmvw-Gm5DCuqVw3V7wIAR1jyruqOglKV3xpQ5naXbw6tH2oQ9xznShrqbShouwN-ZD2VFbeKlre2fqlFrLH5WTvWD6DB1t7XnLJ2PLk-RLLT-T8mD84bS033s-rJXfDnPU72ceoU5HqLMSZ6-iNq36oK4pWwvFdwAHqD959qawkxz54HUATYYruIRlafraXNOvi-azn-71eyLj80u4nbr7JdxwXhqkpnGVo6hK4Yua31BrjzA_C_YvN_kzOvXgCu_bhzwKDzJQzFlOsuO9-sWN_3Z3GvQ2sC5v-0mXbY-U2Y3WJEYhQTxAKkaQqoTiL4B0HQ65hk7ZN_1IOFnYTyJ7OMOjLW-hOnl1jXD9rjGmSTo02fCgy2Okg4RCBkn9Cd5BXreX0YN7Y1BpnI7shsdumOXR65jeC56IhC29Ixvtkr7uXxIVZUR2xTZ7v2JrasL202gH6urq4fpcK8efvt_07rSWtjs3737vkpawWEwO8_f-7GynesYphRsq1F-oRRLlw6x5fLRW1SzP4HIpRcmW1lHjljuVvuSoidl2d8bWXYaHQU44doqT5HDu5LsnYxL8WqTr2IeTr65VCEdRnZj9WdRnqnrgOW3toJjnUsENd2tdQUDQnz04IF1pFEGXd_M-K_v1DBAEfXYOhe0L5Zjh1IWzGnglFIdhA7-ricO7mjoLdQ0rUdfccOX6upSwBvN-_ZiIiHSXoWSku1RPj_m-3dOBzyGjrfV9ujU_Krjjxmgz_Uw52es1K6XU4VQzQbwmKanyCEdJXOGE5RFiJOVlTUqckITkcVajP7GfjeMrjHOUT_yfqDipTuOqiAt6wk8jkkWEJGmOTtanKWU0Tuo8ximleRTVGalzFiU4r3maF_hEnGKEceR_4ohgNI1z6hVMC8ZKVmACEsQ3VMipV3WqzeokVOacpgVJshNJSy7trs7SnAZCynZlQYL8eswePnPCyVCRuUOXzj-po3yxWHJfJDmsPjwP9SxwlkXopDXy9NurjAKc_wUAAP__Bacnlw">