<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/59564>59564</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Register Allocation missed optimization on x86
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          tyb0807
      </td>
    </tr>
</table>

<pre>
    Given [this input IR](https://github.com/llvm/llvm-project/files/10250293/ll.txt), the generated asm code contains the following
```
     41a:       c4 42 7d 18 0c be       vbroadcastss ymm9,DWORD PTR [r14+rdi*4]
     420:       48 8b 7d d0     mov    rdi,QWORD PTR [rbp-0x30]
     424:       c4 62 3d a8 c8  vfmadd213ps ymm9,ymm8,ymm0
     429:       c4 a2 7d 18 04 0f       vbroadcastss ymm0,DWORD PTR [rdi+r9*1]
     42f:       48 8b 7d d0     mov    rdi,QWORD PTR [rbp-0x30]
     433:       c4 e2 3d a8 c1  vfmadd213ps ymm0,ymm8,ymm1
     438:       c4 e2 7d 18 0c 0f       vbroadcastss ymm1,DWORD PTR [rdi+rcx*1]
     43e:       48 8b 7d d0     mov    rdi,QWORD PTR [rbp-0x30]
     442:       c4 e2 3d a8 ca  vfmadd213ps ymm1,ymm8,ymm2
     447:       c4 a2 7d 18 14 17       vbroadcastss ymm2,DWORD PTR [rdi+r10*1]
     44d:       48 8b 7d d0     mov    rdi,QWORD PTR [rbp-0x30]
```
Notice the `mov    rdi,QWORD PTR [rbp-0x30]` instruction is repeated for no good reason. After some investigation, [here](https://github.com/llvm/llvm-project/files/10250322/mir_bef.txt) is the MIR before register allocation, and [here](https://github.com/llvm/llvm-project/files/10250326/mir_aft.txt) is the MIR after it. These duplicated instructions are inserted during RegAlloc.

@qcolombet Please take a look.



</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyslc-O2zYQh5-GvgxikEPKlg462DFc5NA2NQL0WPDPSGYjiS5JO7t9-oLajbveOECLrGFIsEf66ftmQEqn5PuJqGXVllW7hT7nY4htfjS85uuFCe6x_clfaAJWbfPRJ_DT6Zzhw4FVO4b1MedTYnLDcM9w3_t8PJulDSPD_TBcvp7enWL4k2xmuO_8QInhXnCsODZyvmKZHzLDhuF7yEeCniaKOpMDnUawwRHYMGXtpzTXuzAM4YufesZ3jG_Yij9_559QPkroQsUbq0AhrB2IGrgFQ6XKeHMxMWhndcopweM4lofvfv_1sIOPnw5FNgrFcBudZ7hRRfZFOPKncFVDbUq44yVzDJdSnu95_9tNmDm94w-Sv85RV8gVgnSga7D1jNeN2jkU8nSlexzH-ul0I4rNNUNfRRXw7p4l_8aysG5jw3AjXsN1byMp5RWQrpLijiS_kRQ3GfXLjOs070uK70jahzuWkt7GUuEdS33HUtxY4k3G-ttRCgVifc8Sv2Mp-B1L5X7U8tUi-yVkb2lejWzF_1vOioOfUo5nm32YwCeIdKJ5nXchwhSgD8FBJJ3CtIRNlylCCiOBny6Usu91ubHsEqzaHinSW-xBEpHhfvTxD0Pd80ZU2Irazx8OYKgLkSBS71MB0sMQ7BVET-5tYVbPMLrLd2D03BOfl_DpSInAnU-Dt3MLX7Q2gY6laYliqbhz9FMPB-o3hX35PNCno-J_2TCE0VCGjwPpRJD1ZwINQwifb6-djwvXStfIRi-oFau1QFlXslkcW1RoulpJbbTGpjG8slZ2ol5ZrKWWduFb5IgCxZrzqpLN0prGNOvKNOu1aozumOI0aj8sS4uWIfYLn9KZ2qqpVmoxaENDml9UiBN9gbnIEMt7K7ZzW825T0zxwaec_k3JPg_UHr5OcHOdIIw-JXIQTtmP_u-n_8IED_VqcY5D-7-HOSOVac7I_wQAAP__uDMlAA">