<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/59547>59547</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            AMDGPU codegen wrongly sets ABS/NEG bits in V_PERMLANE instruction encoding
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AMDGPU
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          jayfoad
      </td>
    </tr>
</table>

<pre>
    The binary encoding of these instructions is wrong:
```
$ llc -march=amdgcn -mcpu=gfx1100 -show-mc-encoding < test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll | grep permlane.*op_sel
        v_permlane16_b32 v0, v0, s7, s0 op_sel:[1,0] ; encoding: [0x00,0x00,0x5b,0xd6,0x00,0x0f,0x00,0x20]
        v_permlane16_b32 v0, v0, s7, s0 op_sel:[0,1] ; encoding: [0x00,0x00,0x5b,0xd6,0x00,0x0f,0x00,0x40]
        v_permlane16_b32 v0, v0, s7, s0 op_sel:[1,1] ; encoding: [0x00,0x00,0x5b,0xd6,0x00,0x0f,0x00,0x60]
        v_permlanex16_b32 v0, v0, s7, s0 op_sel:[1,0] ; encoding: [0x00,0x00,0x5c,0xd6,0x00,0x0f,0x00,0x20]
        v_permlanex16_b32 v0, v0, s7, s0 op_sel:[0,1] ; encoding: [0x00,0x00,0x5c,0xd6,0x00,0x0f,0x00,0x40]
        v_permlanex16_b32 v0, v0, s7, s0 op_sel:[1,1] ; encoding: [0x00,0x00,0x5c,0xd6,0x00,0x0f,0x00,0x60]
        v_permlane16_b32 v0, v0, s2, s3 op_sel:[1,0] ; encoding: [0x00,0x00,0x5b,0xd6,0x00,0x05,0x0c,0x20]
        v_permlane16_b32 v0, v0, s2, s3 op_sel:[0,1] ; encoding: [0x00,0x00,0x5b,0xd6,0x00,0x05,0x0c,0x40]
        v_permlane16_b32 v0, v0, s2, s3 op_sel:[1,1] ; encoding: [0x00,0x00,0x5b,0xd6,0x00,0x05,0x0c,0x60]
        v_permlanex16_b32 v0, v0, s2, s3 op_sel:[1,0] ; encoding: [0x00,0x00,0x5c,0xd6,0x00,0x05,0x0c,0x20]
        v_permlanex16_b32 v0, v0, s2, s3 op_sel:[0,1] ; encoding: [0x00,0x00,0x5c,0xd6,0x00,0x05,0x0c,0x40]
        v_permlanex16_b32 v0, v0, s2, s3 op_sel:[1,1] ; encoding: [0x00,0x00,0x5c,0xd6,0x00,0x05,0x0c,0x60]
```
These instructions do not support the ABS (bits{10..8}) and NEG (bits{63-61}) fields, which should be set to zero, but they are not.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJy0lt-PozYQx_-a4WUEss2v5YEHkmz2pXc6tde-RgYb8NVghM3upn99BcmlOXWjJk1OijyCie3PzJfRDLdWNb2UOcQriDcen1xrxvwb39eGC680Yp9_bSWWqufjHmVfGaH6Bk2NrpVWouqtG6fKKdNbVBbfRtM3EBZANkAKSMjxd3hkEWpdod_xsWoh3PBONFWPflcNE4Sbpn6nlBD0bWve_K7yT_dBuEYnrQO2XRshX2QPbFt82rx8-R3YVuvXLjicFQxy7DTvZaA1QrrGZpQDnl4CK8yws1IfgUj2uvvupMmuDBm-EmDr42rTZSV43BQWEK8osDWBeIMQrk4ZgbBAiFfkncwbTyYuFyOS85ekPn9i81l34Mwe-jic6E4c-lic5ALO-09Rq_rfal3Nc5Nc_81zSa6b8vNAnkt6fYTDljV8cHHFB1PdXFwf4dxfXD_g3FJcl7LzQJybiututT78eK5S62qe-4vrKrluys8Dec71-rGzfv13MxYGe-PQTsNgRje3ayxWvyGwp1I5C-mKkiB4gnQDLEPeC_z8_HLmTUI_oUdvraQWdo7vrVVVi7Y1kxZYSrTSoTP4lxzN7C6n5aI98lHOtweeyEORhRn3ZE6TlNKMEhZ5bS5CRqO4zp4qwkkUybqOWJI-1YnIaiIj7qmcEcYoowmlURhFAU9LwtIsEymnIstqiIjsuNLB0v3N2HjK2knmcRZHqad5KbVdxhrGSl79KXsBYfF9ZGDzsDPm81a_nBoLEdHKOvvPYU45LfPD_7EyQjayP0w3ej-HbedsAtvOWZtThqrHP3Zfnn_99Evx-flcipPw3jTqvHVusPPXwbbAto1y7VQGlemOY8zR-MNovslqnneWqCyw7RLY3wEAAP__M76zJQ">