<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/59343>59343</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AArch64][SVE] Missed optimisation for _x variants of multiply-accumulate intrinsics
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Sevenarth
      </td>
    </tr>
</table>

<pre>
    There is a missed optimisation which affects all of the following intrinsics in their predicated "don't care" form: [svmad](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmad[_s32]_x), [svmla](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmla[_s32]_x), [svmsb](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmsb[_s32]_x), [svmls](https://developer.arm.com/architectures/instruction-sets/intrinsics/svmls[_s32]_x) and their negated counterparts: [svnmad](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmad[_s32]_x), [svnmla](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmla[_s32]_x), [svnmsb](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmsb[_s32]_x) and [svnmls](https://developer.arm.com/architectures/instruction-sets/intrinsics/svnmls[_s32]_x). This is related to the case when a second or third operand is placed in the same register used to store the result.

This behaviour can be reproduced by shifting the arguments in a shim function as follows:
```cpp
svint32_t test(svint32_t op3, svint32_t op1, svint32_t op2) {
    return svmad_s32_x(svpfalse(), op1, op2, op3);
}
```
which compiles to:
```asm
pfalse  p0.b
mad z1.s, p0/m, z2.s, z0.s
mov     z0.d, z1.d
ret
```
whereas gcc 12.2.0 compiles it correctly to:
```asm
pfalse  p0.b
mla     z0.s, p0/m, z1.s, z2.s
ret
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJy0Vs1u4zgTfBr60oggU5J_DjrE48-37zSDvQYU1bK4oEihu-VM8vQLSspmNtkMsAcDQWx3y1XVZLFow-yuAbFW1UlV542ZpI9Uf8cbBkPSb5rYvtQ_eiQEx2BgcMzYQhzFDY6NuBjguXe2B9N1aIXBeA-xA-kRuuh9fHbhCi4IucDOMriQeo5gJGydNYItKK3bGJTeC1hDqLSGLtKgikdQ1Ylvg2lVdVb60IuMrIpHpS9KX1q8oY8jUmZoyGwclL4Ysr0TtDIRstIXF1hosknoA6MspTcxSl9W8NMTF1pV56efSh-V_rbyenNH3gT-BS83d-RN4F_Ny_eclz_wggntaoaA19kJNk5BkEZDwn9vf7jr_offGCDc1QHhNxYId_VA-GyCeTPehr6jDcJnH2Two3ecAobQzzaQOAeINYzw3GMAA4w2hhYigfSOUgQhJcmOYfTGYrsmC7AZEAivjgUJJl7gWCLh3CfkyUum8rPKH5f_M32Dvbm5OBFYE6BJD44U2ylBNy_AveskZVnCMHSdBgwyx5lJvQG6Kcxzg-E1-ealW2h2-fJnx3Gp8M0FKfSTgCCL0of3QhyLZINfC9uPBZ12TO1PCxgAAKFMFGDOs7S4aWUPfBs74xmVPqzmWrFmhG8L1VEVK47anz_oXT4uCW_jMDqPDBI_D2Z4WCoLIcCYZ81SGUwLr9uME-GYK30Z0rtXvVRe84zX5-ItDZIq7dzZZu3SIZQvdCGhYbhaC1ud6Sx_F-kEbCRCK_7lPyv25k3JR9XrHLP6L7Rt2rpoj8XRbLDe7va5ro6Hcr_p60Onm0NXteXueMBttetKrI6IW-x2tjLb3cbVOtd6q_Nqu8_LvMxMXpZoOquLo-5MsVNljoNxPvP-NmSRrhvHPGFdHYuy2HjToOf5Ltc64DPMTaXTQdtQnb7z0ExXVmXuHQu_o4gTP_8IeHwk2-_KdPyr0_c__qeqM_z_X-78LhI8_YSbIWfSMYgdDJMXN_qXB2PtNEzpIP9y728m8vU_8-TqpJ-aNUiSlPXlYaT4J1pJ2ZEGSLkxD_hXAAAA__9NKtAO">