<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/59318>59318</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [MSP430] Backend crash with machine code errors
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          HazyFish
      </td>
    </tr>
</table>

<pre>
    ## Description

The following code crashes `msp430` backend with 2 machine code errors:

- Reading virtual register without a def
- Virtual register defs don't dominate all uses

The problem doesn't exist when targeting `x86_64`, `aarch64`, `riscv64`, or `wasm64`.

## Minimal Reproduction

https://godbolt.org/z/Ts66Yq3sf

### Code

```ll
define void @f(i1* %0, i1 %1) {
BB:
  br label %BB1

BB1:                                              ; preds = %BB4, %BB1, %BB
  %P = phi i32 [ 0, %BB4 ], [ 1, %BB1 ], [ 0, %BB ]
  %B3 = lshr i1 %1, true
  br i1 false, label %BB1, label %BB3

BB3: ; preds = %BB1
  switch i32 %P, label %SW_D6 [
    i32 3, label %BB4
    i32 5, label %BB2
  ]

BB4: ; preds = %SW_D6, %BB3
  br i1 true, label %BB1, label %BB2

BB2: ; preds = %BB3, %BB4
  ret void

SW_D6: ; preds = %SW_D6, %BB3
  store i1 %B3, i1* %0
 br i1 %B3, label %BB4, label %SW_D6
}
```

### Stack Trace

```console

# Machine code for function f: NoPHIs, TracksLiveness, TiedOpsRewritten
Function Live Ins: $r12 in %1, $r13 in %2

bb.0.BB:
  successors: %bb.2(0x80000000); %bb.2(100.00%)
 liveins: $r12, $r13
  %1:gr16 = COPY $r12
  JMP %bb.2

bb.1.BB4:
; predecessors: %bb.2
  successors: %bb.2(0x80000000); %bb.2(100.00%)

  JMP %bb.2

bb.2.SW_D6:
; predecessors: %bb.2, %bb.1, %bb.0
  successors: %bb.1(0x04000000), %bb.2(0x7c000000); %bb.1(3.12%), %bb.2(96.88%)

  %4:gr8 = AND8rc %4:gr8(tied-def 0), 1, implicit-def dead $sr
  MOV8mr %1:gr16, 0, %4:gr8 :: (store (s8) into %ir.0)
  %5:gr16 = SUBREG_TO_REG 0, %8:gr8, %subreg.subreg_8bit
  BIT16rc %5:gr16, 1, implicit-def $sr
  JCC %bb.1, 1, implicit $sr
  JMP %bb.2

# End machine code for function f.

*** Bad machine code: Reading virtual register without a def ***
- function:    f
- basic block: %bb.2 SW_D6 (0x24c70c0)
- instruction: %5:gr16 = SUBREG_TO_REG 0, %8:gr8, %subreg.subreg_8bit
- operand 2:   %8:gr8

*** Bad machine code: Virtual register defs don't dominate all uses. ***
- function:    f
- v. register: %4
LLVM ERROR: Found 2 machine code errors.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: ./llvm-project-latest/build-debug/bin/llc -mtriple=msp430 ./crash-reports/dagisel-msp430/1.ll
1.      Running pass 'Function Pass Manager' on module './crash-reports/dagisel-msp430/1.ll'.
2.      Running pass 'Simple Register Coalescing' on function '@f'
 #0 0x00007fc19ea0f29a llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/Support/Unix/Signals.inc:567:11
 #1 0x00007fc19ea0f44b PrintStackTraceSignalHandler(void*) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/Support/Unix/Signals.inc:641:1
 #2 0x00007fc19ea0dac6 llvm::sys::RunSignalHandlers() /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/Support/Signals.cpp:104:5
 #3 0x00007fc19ea0fb75 SignalHandler(int) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/Support/Unix/Signals.inc:412:1
 #4 0x00007fc19d1cb980 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x12980)
 #5 0x00007fc19c4c7e87 raise /build/glibc-CVJwZb/glibc-2.27/signal/../sysdeps/unix/sysv/linux/raise.c:51:0
 #6 0x00007fc19c4c97f1 abort /build/glibc-CVJwZb/glibc-2.27/stdlib/abort.c:81:0
 #7 0x00007fc19e884514 llvm::report_fatal_error(llvm::Twine const&, bool) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/Support/ErrorHandling.cpp:125:5
 #8 0x00007fc1a2306083 llvm::MachineFunction::verify(llvm::Pass*, char const*, bool) const /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/MachineVerifier.cpp:348:22
 #9 0x00007fc1a206a6ff llvm::LiveRangeCalc::findReachingDefs(llvm::LiveRange&, llvm::MachineBasicBlock&, llvm::SlotIndex, unsigned int, llvm::ArrayRef<llvm::SlotIndex>) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/LiveRangeCalc.cpp:212:7
#10 0x00007fc1a206a5be llvm::LiveRangeCalc::extend(llvm::LiveRange&, llvm::SlotIndex, unsigned int, llvm::ArrayRef<llvm::SlotIndex>) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/LiveRangeCalc.cpp:105:7
#11 0x00007fc1a2045772 llvm::LiveIntervals::extendToIndices(llvm::LiveRange&, llvm::ArrayRef<llvm::SlotIndex>, llvm::ArrayRef<llvm::SlotIndex>) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/LiveIntervals.cpp:627:22
#12 0x00007fc1a24bd02e llvm::LiveIntervals::extendToIndices(llvm::LiveRange&, llvm::ArrayRef<llvm::SlotIndex>) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/include/llvm/CodeGen/LiveIntervals.h:187:5
#13 0x00007fc1a24ae833 (anonymous namespace)::RegisterCoalescer::joinVirtRegs(llvm::CoalescerPair&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/RegisterCoalescer.cpp:3701:3
#14 0x00007fc1a24a8dc0 (anonymous namespace)::RegisterCoalescer::joinIntervals(llvm::CoalescerPair&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/RegisterCoalescer.cpp:3705:50
#15 0x00007fc1a24a5212 (anonymous namespace)::RegisterCoalescer::joinCopy(llvm::MachineInstr*, bool&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/RegisterCoalescer.cpp:2041:7
#16 0x00007fc1a24a2e13 (anonymous namespace)::RegisterCoalescer::copyCoalesceWorkList(llvm::MutableArrayRef<llvm::MachineInstr*>) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/RegisterCoalescer.cpp:3932:10
#17 0x00007fc1a24a2b65 (anonymous namespace)::RegisterCoalescer::copyCoalesceInMBB(llvm::MachineBasicBlock*) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/RegisterCoalescer.cpp:4053:7
#18 0x00007fc1a24a08e0 (anonymous namespace)::RegisterCoalescer::joinAllIntervals() /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/RegisterCoalescer.cpp:4081:29
#19 0x00007fc1a249f5d2 (anonymous namespace)::RegisterCoalescer::runOnMachineFunction(llvm::MachineFunction&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/RegisterCoalescer.cpp:0:5
#20 0x00007fc1a21a5375 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/CodeGen/MachineFunctionPass.cpp:91:8
#21 0x00007fc1a1357b36 llvm::FPPassManager::runOnFunction(llvm::Function&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/IR/LegacyPassManager.cpp:1430:23
#22 0x00007fc1a135c962 llvm::FPPassManager::runOnModule(llvm::Module&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/IR/LegacyPassManager.cpp:1476:16
#23 0x00007fc1a1358409 (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/IR/LegacyPassManager.cpp:1545:23
#24 0x00007fc1a1357f7d llvm::legacy::PassManagerImpl::run(llvm::Module&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/IR/LegacyPassManager.cpp:535:16
#25 0x00007fc1a135cc41 llvm::legacy::PassManager::run(llvm::Module&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/lib/IR/LegacyPassManager.cpp:1672:3
#26 0x00000000004199ac compileModule(char**, llvm::LLVMContext&) /home/henry/aflplusplus-isel/llvm-project-latest/llvm/tools/llc/llc.cpp:736:41
#27 0x0000000000417d52 main /home/henry/aflplusplus-isel/llvm-project-latest/llvm/tools/llc/llc.cpp:417:13
#28 0x00007fc19c4aac87 __libc_start_main /build/glibc-CVJwZb/glibc-2.27/csu/../csu/libc-start.c:344:0
#29 0x000000000041755a _start (./llvm-project-latest/build-debug/bin/llc+0x41755a)
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzUWltz2zaw_jXwC8YaEuD1wQ-SbLXu2I1HdtPpedGAICihgQAdAPSlv_4MQFK8RGmc1nFzNIklgsBiv28XuwuQxBi-lYxdgHgB4sszUtud0hc_k79eVtzszgpVvlwAhAHC8JIZqvnBciVBcAmCefP3YcdgpYRQT1xuIVUlg1QTs2MGgiTYm0OEA5AEsCD0E5MlfOJ2BxHcE7rjkjUDmNZKG4DnQ8HncM1I6YQ-cm1rIqBmW24s016Gqi0ksGRV1_vjtFfJKgNLJQFKLSzVnktiGSRCwNowM8Vw0KoQbA9LxUwzhD1zY-HTjkloid4y63QBSfCcJZskAkkA0NJdE6LpbtiguaGPxwalXdsTMXvfNBtO3FJ7yyXfEwHX7KBVWdMpxztrD54etAJotVVloYSdKb0FaPUXQKsHkyR__C821eeynfilKtnoThI0_4RoGkpWOVs8Kl5CEAUVQBkPAZpDgGKPgYfuZwhQDkG6aAYtFkeDQVhoKEjBhOu2WITD2dwlnsNv-gC8gAfNSgMBvmxkRp7cRnr3q5sdoPjO9zzsOOQYQRAvYHDsFkEQX_qreAH70eGwue_tW3vBC-wlC7PTPQ1LaHXNBuB5CCsiDHO3RkSMr_GYGOyIOYE17CSbJ27proGE4ruRtPvfN5eJ073rDH0_PJkyGt-OJ7fREWqHulMuOqmcn_XIFR5T4En5ewbQeBL0BQZwb7xuCs2s99ChgEabb9DTWKVZa8dmkoGjN30KPbo_ovIz_ltl0svJyjq9EO8toZ_ggyb09HqkShol2GQwvB3GykppWNXSxwhYOey_qrufr43TzUn-ZG74I5PMNC2clR8OZs2eNLeWtVFl1Y13XeG1NJ5CFOkQQS6PPu5bcNsyMlxRzILZKACYmlJmTBPGXf-imCGAsuA5C5oPQLmzUn8rDIKZa47dnUaM4I-MD9Xp1RgsSRdPtjpMvK2XH-7-6Dq3XX65vTtOM1Y6nDV-3Ta3TsNOaP6WsL6uF5p1nvx1zRqfdmD6n8Hf6Rt6fYOo1_c4roGS0hNQ3Cg8cxaIPxuSJ7MsO4UQoDjyxsm8bea_XmaaDloByixn5XnJKthp4mHw_UFwyq2_UzJSOpMa3cm9_fAx2-uh7d2gLmb3U84b1FmzzN2PzOUsLq1yHbmeBb2zuZZ46Er3vy3WVz9tHj5s1lc_HaVnner-ytSFZttZ87XJCm47aYvrhzBp0MYDJT-HN0L2y3JkzlHvSc_T3uMCxJUsxwXVOEhMSo72H1yQ8SjH3etKLngU0hVf3WRtpj8WZQUxnMJCKPpp4MOwzV3O-VBE04D2ZjmHXBqr66O4t7TSOVQHpoksIWo0HYx8NUffWGjOXs_W4-wotEXeZr-bm4-38Gq9_rB27StVOwSnaujW1Hc3V_P7K2jqYs-dzYp6CzU7KG2hVXBSTnK7q4sZVXuAVkI8dl_nB63-ZNQCtOLG1MwAtIKOOi6pqEsG7a4t9X1tb11Wa6dv8lxZ7w_HiObq3vxOq60me0j0tt4zaX2Qmk3mOxfEMuOmLWouXKwoalfoFlz6nhSe763mB8EAvmz2F16GV-W8Qel0LcmWGybO2y0IWoWzrt4NnTLrWkrn6gdiDAQoPSbFO9dwSyTZMg1QCpWEe1XWwgWU9PUzub5-NnRqtnu3yBlcdz60VEQwQ7nctlMely9AaVOTp20kAAgHMHh2ETutaJgzElQoJ9DbzodA82KaH3eaS-ut0RQdKOs7afK0UcZqRvYA-VDFpfUVPlrt1J65Lyb1C0ArUomDqI37f-6QftFinfvwAqDVfX1wDAG0-k3yZ9fAt5IIM-OSAjyPkxTgeRj2qMIpqigq4ARCI-NnIkvhrJP5itAtrnfTO4lcDhqojSZql4Qmp4yxruVIewNQ9n307hSmB7cAw8AlyLhXGE95LtIYTol9X2eIQjQmNRrqWIa0yLMAbjaa-dS-0S45ZkfpzZb8XHBZP59vZd3cONidZqScGeXS_iJ4DlGeDQoAgHA8nIZGNGVZCjXhxi32JgC5ECl4Qc-XH395-p_ieIlmKAVoZTwOgFYzFxrMiynZwQWFuoFpXsyj10bW7tKLnnn3d14U9JokE03ytAohKZRH-jpNbNmw4Uf5SbLJJOnI8lkWxWE0cNUmpG0qYonY-IQyihgPT022kc68PmIUSonv4yVXbnbvjVxuO0dG8diRswEcgnCQBBkewGn3Tas-2wI8f2SaVy8jXC7g-xiyhHRHdIdwPkTo294M51KV7Cfm8lmr40enFWe6RYojV5Ug1EPNR1CDhCRVNYDqNnJrIrdsSQRtmiouyzXz4reXrDIjyMf-rSE_I23hCreFr9umPe6FsteyZM-uuZb-BLFsksew21xr8rJmFcDLU2Px1Vs6Tk_oiImWTuSjS3osmMNgymZcsL9nkz1bJstXcvj_j6EwiMcMhWOGojhN0YSha2mZfiTCDBl6UNey5JS91t1ewcEPQtkRbktZgtLBGnWcoRFnUVEGaOpV78XZW5DQ1vl9w5f42DkHytI-Njsy8JgMwjKMXc4mUsmXvaoNlGTPzMGXpXlbIbXVcFsM-10QwPM_FZdu07Vm2zFFx353hGtP0_cw_mdadUE6DVx6xT3maII5K2nwLzD3zvJDgfZJOOhRxxPUMQrRv0C9VIdxem4z0rU0Vo-y8jtDR4Gv_AdBMpkgRyz8pz5O1eGla_pd6U833Kk4ZKG2pBDs5NqfMvS9wuAXnSLHvnwfOEU6paZI4jeg5lreLhanvGNYr7zpbvDr6KMgxmO_yCbgg4z9mzgwF2IYCt4bnd9EHE96EQ7HtWiUV3H5Txe8ruUHOa3TT5i3v_fOiz4YZTU0LhxDEuM0_vKOw28sepwnAX53ZCd0arHlzrBZD25U84U4Tgs8PMhY3bmx3cHYfwPreu2qD7Yl9GWgTFfERtiZC_UZGaEJJJon6BWQbv1539gR26b3hJMm7ivp4eAJnCwK8q-tvNsfGmMcxROTRVMvrNJyYDLhJfUb91be9f4gjuD-Y1Axjid2i6duSKPw65h-FDxhkqJRoYu6wqf5RGGeEwqp2h-4YEe_ojuiu0cfw-3Lzc3H26WSlj3bN0NhlXK5cSUEbf62qqc48aeLverpRPW0jBHcE_-Q-3tpEYX-qHtAYDY-7SOEZincbAQv6MZYou2mU-k1J3_U1N0BZPPT3_Ry_DEgjqL-HNBNn09JiGMCm4ldOPnmRzL-dLUR0z8T7t5qOCsvcJnjnJyxizBJgwDncZaf7S6SKKVFGNGwylkRBxULsiAMC0pImGclQ2f8AgUIhSjAAY5xkM-yKCUsqaIkrAiLKwaigO0JFzOn7Uzp7Zl_VHUR5zjMzvyrGsa_24aQZE_Q3wQIgfjyTF94hEW9NSAKBDfW9FIst8K_FHd7f-eSSnwJF-37a80TL_8W24nnb2e1Fhf__Pma1_v_AgAA__8pjuPb">