<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/59250>59250</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Segfault when compiling for AMDGPU backend with alloca instructions using the default addrspace
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Raphalex46
      </td>
    </tr>
</table>

<pre>
    Hi, 
when compiling LLVMIR containing alloca instructions using the default addrspace for the `amdgcn-amd-amdhsa` target, `llc` segfaults.
Using `addrspace(5)` instead of the default one solves the issue, as it seems to be the correct way to use `alloca` for this target, however, `llc` should probably stop cleanly with an error.

Here is a reduced test case that causes the bug : 
```llvm
; File test.ll
define  ptr @test_func() {
  %1 = alloca i8
  ret ptr %1
}
```
First, I generate LLVM bitcode : 
```sh
clang -target amdgcn-amd-amdhsa test.ll -emit-llvm -c
```
Then, I call `llc` : 
```
llc test.bc
```
And it crashes with the following stack trace :
```
llc: /home/racolin/microcard/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:497: void getCopyToParts(llvm::SelectionDAG&, const llvm::SDLoc&, llvm::SDValue, llvm::SDValue*, unsigned int, llvm::MVT, const llvm::Value*, llvm::Optional<unsigned int>, llvm::ISD::NodeType): Assertion `NumParts == 1 && "No-op copy with multiple parts!"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: llc test.bc
1.      Running pass 'CallGraph Pass Manager' on module 'test.bc'.
2.      Running pass 'AMDGPU DAG->DAG Pattern Instruction Selection' on function '@test_func'
#0 0x00007f81286982d2 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /home/racolin/microcard/llvm-project/llvm/lib/Support/Unix/Signals.inc:573:3
#1 0x00007f812869643c llvm::sys::RunSignalHandlers() /home/racolin/microcard/llvm-project/llvm/lib/Support/Signals.cpp:103:20
#2 0x00007f81286965ce SignalHandler(int) /home/racolin/microcard/llvm-project/llvm/lib/Support/Unix/Signals.inc:407:1
#3 0x00007f812ab5a140 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x13140)
#4 0x00007f8127fc3ce1 raise ./signal/../sysdeps/unix/sysv/linux/raise.c:51:1
#5 0x00007f8127fad537 abort ./stdlib/abort.c:81:7
#6 0x00007f8127fad40f get_sysdep_segment_value ./intl/loadmsgcat.c:509:8
#7 0x00007f8127fad40f _nl_load_domain ./intl/loadmsgcat.c:970:34
#8 0x00007f8127fbc662 (/lib/x86_64-linux-gnu/libc.so.6+0x31662)
#9 0x00007f812a933288 llvm::EVT::bitsGT(llvm::EVT) const /home/racolin/microcard/llvm-project/llvm/include/llvm/CodeGen/ValueTypes.h:258:7
#10 0x00007f812a933288 llvm::EVT::bitsGT(llvm::EVT) const /home/racolin/microcard/llvm-project/llvm/include/llvm/CodeGen/ValueTypes.h:256:10
#11 0x00007f812a933288 getCopyToPartsVector /home/racolin/microcard/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:737:52
#12 0x00007f812a933288 getCopyToParts(llvm::SelectionDAG&, llvm::SDLoc const&, llvm::SDValue, llvm::SDValue*, unsigned int, llvm::MVT, llvm::Value const*, llvm::Optional<unsigned int>, llvm::ISD::NodeType) /home/racolin/microcard/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:483:32
#13 0x00007f812a975c0c llvm::TrackingMDRef::untrack() /home/racolin/microcard/llvm-project/llvm/include/llvm/IR/TrackingMDRef.h:89:9
#14 0x00007f812a975c0c llvm::TrackingMDRef::~TrackingMDRef() /home/racolin/microcard/llvm-project/llvm/include/llvm/IR/TrackingMDRef.h:55:29
#15 0x00007f812a975c0c llvm::TypedTrackingMDRef<llvm::MDNode>::~TypedTrackingMDRef() /home/racolin/microcard/llvm-project/llvm/include/llvm/IR/TrackingMDRef.h:106:26
#16 0x00007f812a975c0c llvm::DebugLoc::~DebugLoc() /home/racolin/microcard/llvm-project/llvm/include/llvm/IR/DebugLoc.h:33:9
#17 0x00007f812a975c0c llvm::SDLoc::~SDLoc() /home/racolin/microcard/llvm-project/llvm/include/llvm/CodeGen/SelectionDAGNodes.h:1091:7
#18 0x00007f812a975c0c llvm::SelectionDAGBuilder::visitRet(llvm::ReturnInst const&) /home/racolin/microcard/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:1990:40
#19 0x00007f812a97c97b llvm::Value::getValueID() const /home/racolin/microcard/llvm-project/llvm/include/llvm/IR/Value.h:533:12
#20 0x00007f812a97c97b llvm::Instruction::getOpcode() const /home/racolin/microcard/llvm-project/llvm/include/llvm/IR/Instruction.h:157:49
#21 0x00007f812a97c97b llvm::Instruction::isTerminator() const /home/racolin/microcard/llvm-project/llvm/include/llvm/IR/Instruction.h:160:50
#22 0x00007f812a97c97b llvm::SelectionDAGBuilder::visit(llvm::Instruction const&) /home/racolin/microcard/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:1128:22
#23 0x00007f812a9f1d98 llvm::ilist_node_base<true>::getNext() const /home/racolin/microcard/llvm-project/llvm/include/llvm/ADT/ilist_node_base.h:43:45
#24 0x00007f812a9f1d98 llvm::ilist_node_impl<llvm::ilist_detail::node_options<llvm::Instruction, true, false, void>>::getNext() const /home/racolin/microcard/llvm-project/llvm/include/llvm/ADT/ilist_node.h:75:66
#25 0x00007f812a9f1d98 llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Instruction, true, false, void>, false, true>::operator++() /home/racolin/microcard/llvm-project/llvm/include/llvm/ADT/ilist_iterator.h:157:25
#26 0x00007f812a9f1d98 llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Instruction, true, false, void>, false, true>, llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Instruction, true, false, void>, false, true>, bool&) /home/racolin/microcard/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:672:79
#27 0x00007f812a9f32c0 llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) /home/racolin/microcard/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1591:33
#28 0x00007f812a9f4d60 llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) (.part.0) /home/racolin/microcard/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:465:22
#29 0x00007f812a17498c llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (.part.0) /home/racolin/microcard/llvm-project/llvm/lib/CodeGen/MachineFunctionPass.cpp:87:3
#30 0x00007f81289d80ec llvm::FPPassManager::runOnFunction(llvm::Function&) /home/racolin/microcard/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1440:7
#31 0x00007f8128ef08e2 RunPassOnSCC /home/racolin/microcard/llvm-project/llvm/lib/Analysis/CallGraphSCCPass.cpp:179:17
#32 0x00007f8128ef08e2 RunAllPassesOnSCC /home/racolin/microcard/llvm-project/llvm/lib/Analysis/CallGraphSCCPass.cpp:477:21
#33 0x00007f8128ef08e2 (anonymous namespace)::CGPassManager::runOnModule(llvm::Module&) /home/racolin/microcard/llvm-project/llvm/lib/Analysis/CallGraphSCCPass.cpp:542:35
#34 0x00007f81289d8b2e runOnModule /home/racolin/microcard/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:1552:7
#35 0x00007f81289d8b2e llvm::legacy::PassManagerImpl::run(llvm::Module&) /home/racolin/microcard/llvm-project/llvm/lib/IR/LegacyPassManager.cpp:535:55
#36 0x00000000004129ff compileModule(char**, llvm::LLVMContext&) /home/racolin/microcard/llvm-project/llvm/tools/llc/llc.cpp:737:66
#37 0x000000000040a9d6 main /home/racolin/microcard/llvm-project/llvm/tools/llc/llc.cpp:418:35
#38 0x00007f8127faed0a __libc_start_main ./csu/../csu/libc-start.c:308:16
#39 0x000000000040b34a _start (/home/racolin/microcard/builds/llvm/bin/llc+0x40b34a)
Aborted
```

The following version of the code does not crash the compiler:
```llvm
; File test.ll
define  ptr @test_func() {
  %1 = alloca i8, addrspace(5)
  %2 = addrspacecast ptr addrspace(5) %1 to ptr
  ret ptr %2
}
```

I get this error with LLVM 15.0.2 that was built from this repo (4bd3f3759259548e159aeba5c76efb9a0864e6fa).
I also tested and got the same error with a more recent version (15.0.5).

I originally got this problem because of MLIR not reducing `memref.alloca` operations to `alloca` instructions using `addrspace(5)` for ROCDL : https://discourse.llvm.org/t/memref-alloca-in-amd-gpu-kernels-seem-to-lower-to-llvm-alloca-with-an-incorrect-address-space/66864

Please let me know if any information is missing, thank you !

</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzVWttS47oS_ZrwokrK98tDHkIysKmCGQqYeU3Jtpz4YFsuyQby96dbcuILGZgL5OxDhcSW5dbq7qVWW-6IJ7v5P9nEWpKJsZoYi-ctK0nMiyrLs3JDrq9_3FzdQUNZ06zEFprnPKYkK2UtmrjOeClJI_FKvWUkYSlt8prQJBGyojEjKRfqysQzaJFs4nIKP_i_lRTaSE3FhtUKgGfkeYxtkm2UGDnToL4r-ShhL3ZiBe7ECrEzImE0ITwdIOAlI5LnT0yq5kzKhuEoVJKshhFYARc4iZi6HHMhWFyTZ7rD1kZqwEpXHERrkcke3C1_Zk9MjJBveZMnpBI8olG-I7LmFYlzRks4ec7qLaElYUJw0aqmv_9hAiESSgRLmpglpGayJjGVCI_iEUDSmkQNmMJetP6CQfUnz5-Ktsk-JxdZzpSMWZ7rVrBLBiYhVS3IxDHw2jptyhgsCYYkE_9c9yNkYrkmjLA6uDrYXxGs1vdDj3YsfzXCoU8vMiGVla7IhpVM0JopLpEoq2OesGMayK1uiHMK3p5qS5NXpNmrRaasyOop6k2m8VEUD0BmDSIGXXpuOjK6PoXrWn50XOKiTJA-saByC_5QHkWnpBxs9YwslTWNH0ktkPswzM9GUQisiy0vgJUX0JvDfIOjIosFGF0kcIyqTYFK_wFmtqf4k0XwvQQjXqJ2F_csZ2oerhaXo9PzJssTJmZxVcF4TujjqE88S8Ap9ZJXuwd-S0UtgQNKOMC1F0N5HtoPpj-wsddldc3j9lq_9QfN9SQ70rjA9qaU2aYEemdlPex38-Ph2Ej9m7vWbxXio_nEXg4k2l-G_a7uV_rgK1jrYVcxDBlggoWUTKAIpMTXplBGQMoj64H7qJkHP9ZXPsX5C5bSri4gsmQVTK1Km82EPhPLJymF-Za0U_r2-svi_guRTQT8hCmNE1awiosaQ8u2riuJqKwL-GxAahPNIOD2HDx0u4pcMNYFhA5UM86bpA1ayEISAd8U3drh7xUBk6aoDvQzZkT93Qq-EbQgMLOagpU14iCvKG-2ve-aUkX8ikowjuUvYQ5dClptyS223NCSbjD--RBrScGTBuwCZ3tZlt8Csn4ib3Gzurz9ToBmU_Ac_IDcumaiJFfd4kIOdGwHwpilXWf5wzjmt3PNsg1ivBjw56eBaQVeGFiJ1aOF3El9cCuANcpeD0IvKl0nQZ_XHGAwWrRMV5wN_2rW3jcV8gCOvpfZCzYAeWkuZ-BWGNP1bfi2D3qYIz08x46P6QGW1YL-AYrkTMh9UP8QqHuMOoqYBmK0jANIawzShcg3gANoPt92joHRzTzAsvuwaORS0zHIei2AL1ywNUxGZaRW-EvgrT1nCoial-mmbPSFqt6C_5OZ5DNjYp0bL6YNUjCI7Edx-qP4aWzHzCSCZrBuz0CGVBDhYKbOdjJhFU7lRmsADU9qJBhV2QTumykimANd3OEoNHFtn9AII4qSWydaC9WkBAQooJsQ3liAY6S4Bqw1pDUkXBgP1k8YbpVMcBjizjlNCrmJqRbrGhg_g4Nc_5jcdZmv8b51wgtIGt8QF_oG8t05yAuG8qLY86xf8FOMHvKUh2wTbul7KBzwILRtKwh6c-gLrDvqABITefkwCAF4DUir16Q_o24brruGbt1WSxsuSnK2xRnlBgOXmcb_DXBPhYUOuXkM-TDj-AGDcXHqDMi3MUa4VgfVeh_qe8nRKC3SVv-U5GiUFu1H-sDk6OQpaaAWvJ5DhmE79N3Y6C95uE4_QhJxs7pjqW5qSsx-Hv9qyXvF9qs7-BoMprgeYPjrYovp_Dbaif9l2HoK2K6L87SH230HN7AhGYFf9ui4QsogoQ4qvb7hFHqZBoYemGoHxby3FVsxSMbx2WUP_NDw8XD3ohVS2x4Sx38bp37A2oNsH7c-EuHxuYpula1lw2EGYQbvIH49x_WFp0xm9R1umfTCKJw3osQ0vxcuTx59zDA0VObYaTnKFvw49KNXj6PqEBYJdXa1aj3zoautYpCSryew4o_ZxUnLeBto7wnqAPdbhTsvn4a2N6SmkIuLrdOR3jJ_E3MmH5gospJCqnA62J6hEt0OtvU27LeZP6B9_7n2f8l7eE7DuNmj02jZTc0k7CebWZ7BY3YJQ60jKmEGLEGPbgUAcn1lL_Vn-GixesDm4fjKUQ5OCcftdHB-WYesqPLBiqavJaymWa5bVD-uUik56NpnKeRTyg7wm8KTqDrA7TVlmNPbRpnFx7Xe65ZEy_0Vs2Q17tHCNPtkq_TbBhTiVQvAOlefj1zs-nbaK9oLUVaPQ97bxurPqSs46beeU5nF5zlXqei_yb6DrP9fASfiPD9V6EM3tXHP8y2cIL0VaZSGpbYVG7_o7kWedx4fPiRe7LcoTxrje4qarsre7G4n0Rqlb6mTeO9rKpryW3lD421Wsr1SA01fXWtVDWa4QY6bZqdV3PHc0cI2TOhM3wmDfto6UgA3tnuqH9X5BMoeQdUqGGDA6tw62ukOk8BgffUubvHe_U797yr256qozOqabWi86wHYs9NxjMGzxWifm6VGwCx8XYD3fivvl8u_ArMoab6TGe67Hl5hgMyeVU0_VN8dIusniGDW433sJLAcXy1PvT1t-xgscCItebkreCNJSQvWviEPtVuXl8c5cKPe2Aync9v01_5_XzfXwVhsd0vvcCsdqRxZjPSQfiIhXdcaEtI9hqWzU64E6eOeuCuVVrYG_hzDvqmHa2P0c3s23acz-s8xrTBN2-oOdvB_vKVC7SKONhLxff2Sl7XKXv8CeQ2rvVSnsf4e7Mb2UtXD64QWrkHDxCPqHcLHjuyYwYh8oxcPlCUGJes1vltYyxrC-_rwKiOW-NZh1h1ip6nqpF5q2EagHiM74eFIrch2QLi6o3258aZuET68yU6rSPVQOp0bL1rc4Y3HAl8BseRo2cGhKKJXrvDEhMRUpa2eUbUZCWcQSHhb5tC2K86o-HHCuhOs1xmX_HS9Ld173yGmUpenjG_RkmuOF4-UsuyzhZ-UsuhvrGOpdQmQKt_R9QCqpMV0Z8bM0nU6z1QS9FdNUsEL3R_f_aOfnSixU9t3Q8sNXSdgkKVRFlE39j2WRiE1As9hXoq-nO0HheSZK3uyRL3-3_Ba-UNCmO8DoaTgAsIli1lZH5wKgypwbidyL5iLbJNBlM53rUwAilVLOStIxFS5EXLi5vrqTlFB1SW1VVgFKwRLZ111lH54U6VgYOVB4dSROrGf1HFhidXdt-XqWlXnDMskkkzGvBHw5I90m3GxwdmN80RBmerxppmuE9pUzfSRiZLlcoqFXtOaT4HuTKgDjBRtfzTdlJZwX1v_NUVgTMJtGtyF54FT-pa7zRkWZeVABvDAY8mfSZaCa3agKWhQKDNgKVeRSdRWPflsaflIdrwhk_1ifsbmpueFvm14RnCWzO0ktEN6Vmd1zub3bfkbGRXjoYXaogks-mDAB-383yvJO2tEPv_zMhTkr3G2nQd-5Li-4btR4Btm6ltmlJquZ1t2yEwvdM9yGoEH5hMXHuetkj3va_Csibs6y-aWYVkmrEimY8A9s5BFrhsY1DGdJLADB2IFg5ibHzx-JuYKUtRsJFzEh1XZXYTFEF91MTUcyKdNveVifgeJB83Zi-OdqdHnCv1_AS5Hrng">