<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/58609>58609</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AMDGPU][MC] Create tests for VOP3 True16
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            test-suite,
            backend:AMDGPU
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            dpreobra
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Sisyph
      </td>
    </tr>
</table>

<pre>
    For the upcoming support of VOP3 encoded instructions with 16 bit operands referencing hi register halves on GFX11 (part of True16), we need assembler and disassembler tests.

This includes: 

- VOP1,2,C promoted to VOP3
- dpp & dpp8 versions of the VOP3 instructions
- Tests for hi and lo halves of VGPRs

</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJxNkk2TmzAMhn8NXDTJYLMQOHDIJpOcdppp006v_lDArYMZ22Rn_31lkmx3BhBCsvS8EtLpj-7gPMQBYZ6Uu5qxhzBPk_MR3AV-fTuVgKNyGjWYMUQ_q2jcGODdxAFYDdJQ4oRejDqAxwt6Sk9VBkNub0JED4OwNwzgRjgefjMGGW8mce9w9jOyOuNtxnfwjjAidRIh4FVaOkllQZvw_0PEEMM6K_ZZsb0_z4MJxKbsrDFk5Ra-BldJAqPanO4dTN5dXaQO0S3ankl6mgiqTraBG_qwaCS8NJhlCF_FP0-dEwtcaH4kNpFa9ymVZnc8fX-k5tixuq43ZcGqMtddqduyFXk00WKXVa_bt_3x9DOr9vT-tiMLO48i4l3t0mGBuA8rn73thhinpDbjB7p62sYs17RAcqy9Pc2KBP9BFck1Icw0H36omrpo86GTom60UjU2VaFYUxSqbfmFsxfW1BJrkVsh0YbEl3GeSFZhNhHJSbsiI4X6i6MmiocAilT73HS84JwVvOJFWVXlmrUVamRYqUurNxuZvRR4FcauE-La-T733UIr5z5Q0Jq0488gLd_09F88SPTk0UkvHt3EHAfnux8mfExDvqjsFon_ABkz6Pc">