<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/58537>58537</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
"Type set is empty for each HW mode" if all register classes have [untyped] RegTypes
</td>
</tr>
<tr>
<th>Labels</th>
<td>
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
s-barannikov
</td>
</tr>
</table>
<pre>
`$ cat test.td`
```
include "llvm/Target/Target.td"
def R0 : Register<"ar0">;
let Size = 32 in
def R : RegisterClass<"", [untyped], 32, (add R0)>;
def MyTarget : Target;
```
`$ llvm-tblgen -gen-instr-info -I llvm/include test.td`
This results in:
```
Type set is empty for each HW mode:
possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
atomic_cmp_swap_16_acq_rel(ptr, cmp, val): Generated from record:
atomic_cmp_swap_16_acq_rel { // SDPatternOperator PatFrags PatFrag
...
}
Included from test.td:1:
Included from llvm/include/llvm/Target/Target.td:1802:
llvm/include/llvm/Target/TargetSelectionDAG.td:1561:7: error: Type set is empty for each HW mode in 'atomic_cmp_swap_16_acq_rel'
def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
^
Included from test.td:1:
Included from llvm/include/llvm/Target/Target.td:1802:
llvm/include/llvm/Target/TargetSelectionDAG.td:1624:19: note: instantiated from multiclass
defm NAME#_16 : ternary_atomic_op_ord;
^
Included from test.td:1:
Included from llvm/include/llvm/Target/Target.td:1802:
llvm/include/llvm/Target/TargetSelectionDAG.td:1642:25: note: instantiated from multiclass
defm atomic_cmp_swap : ternary_atomic_op<atomic_cmp_swap>;
```
It took me some time to figure out that the reason for this error message is that the register class has `[untyped]` type list.
It would be nice to have clearer error message or none at all.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzVVUtz2zYQ_jXUZUcaCnxJBx5ky059SNuJPZOjBiRXJBqQYAHQrvrruwCpB52kTY_hcEAQj293v30VqjrlQRoGLIaSW7Bo7MpWbiXcB-HOTcbX_4qulEOFEDAm5WsbsMcXrmu0l4m7y9h0148VHuFTCEG0g09YC2NRB9E9HeI6dEejhyC6u70g0cKz-JuERHuIGIjuBmiGcy-5MSOYf-8hSO6Gzp56rIJk7xaicZlteFWRGgHbfi3QAX88jfp7_Mmmy6k5B9dF4syxsLSFrLGDJQ1L0RmraTwqWD7BRNKZtq_Y9eNLIwxoNIO0xlkb7d4LupH-QsaBIUXpDra9PcFRaUBeNvDLZ2hVhZf7vTJGFJLEujul6qzmlSitUB2JAdsg9NwSjx0UKNWbo2kwCMtei84uNZZKVwbehG1mdlpFCiBwKQH_6nlXYQXTYeJ3NQrnVrWiPJRtfzBvvD-s0wMv_zxolCSlt9q5hTbd55VL75cdfMAONbeEd9SqnUAv9nwfEoKMfLUlpumF5_3vo1m_9Q6N6KH_R81rc56MeKvVpGuQ7cfJ0-inSfzZW9FufdFhfmLuXpp9PykIZBOyC84P3nxGid5h-92HCSVJnTaZowu1VtoH7H8GhXN4wLJ_80o2agbg8uHX3ceHgEVXgknKmTyXcBvVG-imaGPx5NDrwuTa68LkZHZ_luKeIHn4eYhPWew-PlA7ZZ1d4LKdd1ZcY7alLBalL0xXOtsLn-vUU-mik-vTYfKH6g8-0O9uybl9fi6iYofCkv9HlKfpXXzCt8miCHx3cFbUv1Wun6i1KfUFWsoTRYMVblBwFPWgEdRA-43rf1QUNXJDJdKlkHWl2acZ3TSG1-hS7Obk2IjA2wENN-DkzppQGo71V9LJ1UWZNzXIisoudKL0ijT8lWq0RK4Jbi6Rpp3qqOBaV3MnjAXm6zRNo80mjjeLKo-qbbTlCyusxJy64Q_0CUa99ejL-NwONKM2Mztc03WYZjFomTfW9sYntqu4NXWIoViVqr2GiW8YvVZ_UHS4MDJmQGoPj8kmibJFkxdZmG3CgpVpFCZJWZRpGhZRmBUZJutimy0kp6ZkclKCpC9EzkLG1iFbs3UcxpsVZiUvtmFG0RYX2ZEHcYgtF3LlBK-Urhc69zoUQ21o09Fvrptkpqg7xDM-H2yjdG6WBde868QX9brwOude4X8A31zceQ">