<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/58530>58530</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [SVE] Crash expanding f128 truncating stores on neoverse-v1
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            SVE
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          mcinally
      </td>
    </tr>
</table>

<pre>
    Here is a crash with f128 truncating stores targeting neoverse-v1:
 
$> cat test.ll
target triple = "arm64-linux"
 
define void @foo(float %factor.arg) local_unnamed_addr #0 {
L.entry:
  %0 = fpext float %factor.arg to fp128
  %broadcast.splatinsert = insertelement <4 x fp128> poison, fp128 %0, i64 0
  %broadcast.splat = shufflevector <4 x fp128> %broadcast.splatinsert, <4 x fp128> poison, <4 x i32> zeroinitializer
  %wide.load = load <4 x fp128>, <4 x fp128>* undef, align 16
  %1 = fmul fast <4 x fp128> %wide.load, %broadcast.splat
  %2 = fadd fast <4 x fp128> %1, zeroinitializer
  %3 = fptrunc <4 x fp128> %2 to <4 x double>
  %4 = fptrunc <4 x double> %3 to <4 x float>
  %5 = bitcast float* undef to <4 x float>*
  store <4 x float> %4, <4 x float>* %5, align 4
  ret void
}
 
attributes #0 = { "unsafe-fp-math"="true" }
 
The assert is complaining about expanding the f128s:

$> llc test.ll -mcpu=neoverse-v1 -O3 -aarch64-sve-vector-bits-min=256 
llc:<scrubbed>/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5278: llvm::SDValue llvm::SelectionDAG::getNode(unsigned int, const llvm::SDLoc&, llvm::EVT, llvm::SDValue, llvm::SDNodeFlags): Assertion `VT.isInteger() && Operand.getValueType().isInteger() && "Invalid TRUNCATE!"' failed.
 
I suspect this store needs to be custom lowered, but f128 seemed special enough in the AArch64 backend that I didn’t want to mess with it.
 
Also note that the IR for this reduced test case is being generated by opt after this patch: [D118979](https://reviews.llvm.org/D118979)
 
If it helps, I could reduce the original IR to run through opt+llc to assist in analyzing D118979.
</pre>
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