<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/58324>58324</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AMDGPU][MC][GFX8+] Inconsistent behavior v_cndmask modifiers
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AMDGPU,
            mc
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            dpreobra
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          dpreobra
      </td>
    </tr>
</table>

<pre>
    `cndmask` opcodes are unique in that they have b16/b32 type, but may be used with floating-point modifiers.
The modifiers work fine for VOP3, but there are issues with other variants:
- SDWA: accepts `sext`, `abs`, `neg`, but fp modifiers are encoded incorrectly.
- DPP64: does not accept fp modifiers.
- E64_DPP: has several problems:
    - using `sext` causes assembler crash;
    - `abs` and `neg` are encoded as expected, but disassembler decodes these modifiers incorrectly.

Examples of passed and failed tests:

    E64 (GFX9, GFX10)
      v_cndmask_b32_e64 v5, -v1, v2, s[0:1]       // ok
      v_cndmask_b32_e64 v5, abs(v1), v2, s[0:1]   // ok
      v_cndmask_b32_e64 v5, sext(v1), v2, s[0:1]  // crashed

    SDWA (GFX9, GFX10)
      v_cndmask_b32_sdwa v5, v1, sext(v2), vcc    // sext is accepted
      v_cndmask_b32_sdwa v5, v1, abs(v2), vcc     // abs is silently ignored
      v_cndmask_b32_sdwa v5, v1, -v2, vcc         // neg is encoded as sext

    DPP16 (GFX10, GFX11)
      v_cndmask_b32_dpp v5, v1, sext(v2), vcc  // rejected by parser
      v_cndmask_b32_dpp v5, v1, abs(v2), vcc   // rejected by parser
      v_cndmask_b32_dpp v5, v1, neg(v2), vcc   // rejected by parser

    E64_DPP (GFX11)
      v_cndmask_b32_e64_dpp v5, sext(v1), v2, vcc dpp8:[7,6,5,4,3,2,1,0]  // crashed
      v_cndmask_b32_e64_dpp v5, abs(v1),  v2, vcc dpp8:[7,6,5,4,3,2,1,0]  // ok, but cannot be disassembled
      v_cndmask_b32_e64_dpp v5, neg(v1),  v2, vcc dpp8:[7,6,5,4,3,2,1,0]  // ok, but cannot be disassembled

One reason for this issue is that current design expects that all variants have the same kind of modifiers (fp/int).
This is not the case with `cndmask` opcodes. E64 have fp modifiers while other variants have int modifiers.

A fix is pending.

</pre>
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