<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/58286>58286</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] 
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          SixWeining
      </td>
    </tr>
</table>

<pre>
    
# Problem
For this test (similar to `llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll`), RISCV generates a `sd  s0, 0(sp)` as the first instruction of prologue which may ruin caller's frame.

# Testcase
`$ cat emergency-spill-slot.ll`
```
@var = external global i32

define void @func() {
  %space = alloca i32, align 4
  %stackspace = alloca[1024 x i32], align 4

  ;; Load values to increase register pressure.
  %v0 = load volatile i32, i32* @var
  %v1 = load volatile i32, i32* @var
  %v2 = load volatile i32, i32* @var
  %v3 = load volatile i32, i32* @var
  %v4 = load volatile i32, i32* @var
  %v5 = load volatile i32, i32* @var
  %v6 = load volatile i32, i32* @var
  %v7 = load volatile i32, i32* @var
  %v8 = load volatile i32, i32* @var
  %v9 = load volatile i32, i32* @var
  %v10 = load volatile i32, i32* @var
  %v11 = load volatile i32, i32* @var
  %v12 = load volatile i32, i32* @var
  %v13 = load volatile i32, i32* @var

  store volatile i32 %v0, i32* %space

  ;; store values so they are used.
  store volatile i32 %v0, i32* @var
  store volatile i32 %v1, i32* @var
  store volatile i32 %v2, i32* @var
  store volatile i32 %v3, i32* @var
  store volatile i32 %v4, i32* @var
  store volatile i32 %v5, i32* @var
  store volatile i32 %v6, i32* @var
  store volatile i32 %v7, i32* @var
  store volatile i32 %v8, i32* @var
  store volatile i32 %v9, i32* @var
  store volatile i32 %v10, i32* @var
  store volatile i32 %v11, i32* @var
  store volatile i32 %v12, i32* @var
  store volatile i32 %v13, i32* @var

  ret void
}
```

# Result
```
$ llc --mtriple=riscv64 emergency-spill-slot.ll -O0 -o -
        .text
        .attribute      4, 16
        .attribute      5, "rv64i2p0"
        .file   "emergency-spill-slot.ll"
        .globl  func                            # -- Begin function func
        .p2align        2
        .type   func,@function
func:                                   # @func
        .cfi_startproc
# %bb.0:
        sd      s0, 0(sp)  ### <---- This may ruin caller's frame.
        lui     a0, 1
        addiw   a0, a0, 16
        sub     sp, sp, a0
        .cfi_def_cfa_offset 4112
        lui     a1, %hi(var)
        lw      t6, %lo(var)(a1)
        lw      t5, %lo(var)(a1)
        lw      t4, %lo(var)(a1)
        lw      t3, %lo(var)(a1)
        lw      t2, %lo(var)(a1)
        lw      t1, %lo(var)(a1)
        lw      t0, %lo(var)(a1)
        lw      a7, %lo(var)(a1)
        lw      a6, %lo(var)(a1)
        lw      a5, %lo(var)(a1)
        lw      a4, %lo(var)(a1)
        lw      a3, %lo(var)(a1)
        lw      a2, %lo(var)(a1)
        lw      a0, %lo(var)(a1)
        lui     s0, 1
        addiw   s0, s0, 12
        add     s0, sp, s0
        sw      t6, 0(s0)
        ld      s0, 0(sp)
        sw      t6, %lo(var)(a1)
        sw      t5, %lo(var)(a1)
        sw      t4, %lo(var)(a1)
        sw      t3, %lo(var)(a1)
        sw      t2, %lo(var)(a1)
        sw      t1, %lo(var)(a1)
        sw      t0, %lo(var)(a1)
        sw      a7, %lo(var)(a1)
        sw      a6, %lo(var)(a1)
        sw      a5, %lo(var)(a1)
        sw      a4, %lo(var)(a1)
        sw      a3, %lo(var)(a1)
        sw      a2, %lo(var)(a1)
        sw      a0, %lo(var)(a1)
        lui     a0, 1
        addiw   a0, a0, 16
        add     sp, sp, a0
        ret
.Lfunc_end0:
        .size   func, .Lfunc_end0-func
        .cfi_endproc
                                        # -- End function
        .section        ".note.GNU-stack","",@progbits
```

Do you have any ideas? Thanks. @llvm/issue-subscribers-backend-risc-v 
</pre>
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