<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/57764>57764</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Hang or crash in RegAllocGreedy for x86
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          VoxSciurorum
      </td>
    </tr>
</table>

<pre>
    The attached IR file causes the code generator to hang (if assertions are disabled) or to crash with an assertion failure

Assertion failed: ((ExtraInfo->getCascade(Intf->reg()) < Cascade || VirtReg.isSpillable() < Intf->isSpillable()) && "Cannot decrease cascade number, illegal eviction"), function evictInterference, file /data/llvm/llvm-dev/llvm/lib/CodeGen/RegAllocGreedy.cpp, line 493.

The IR file was generated by clang -march=bonnell, which may not be a common use case these days.

[hang.txt](https://github.com/llvm/llvm-project/files/9577759/hang.txt)

</pre>
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