<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/57610>57610</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AMDGPU][MC][GFX11] Unclear limitations for operands of v_mad_i64_i32 and v_mad_u64_u32
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AMDGPU,
            mc
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          dpreobra
      </td>
    </tr>
</table>

<pre>
    AMD documentation has no description of limitations specific to these instructions. SP3 also accepts any combination of legal operands for these instructions. However, comments in llvm code seem to require that `dst` and `src2` do not overlap. There is a comment which is even more specific:

https://github.com/llvm/llvm-project/blob/211efaa1ce8164cc27f96acdee7777969e2a2bcf/llvm/test/CodeGen/AMDGPU/mad_64_32.ll#L7

Unfortunately, the way this limitation is specified caused assembler to reject instructions with any dst and src intersection.

My question is: what are actual limitations which should be enforced by assembler? Current limitations look like an overkill to me. 
Added @Sisyph for awareness.
</pre>
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