<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/57532>57532</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [InstCombine] Combine `x < ~x` into `x < 0`
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            llvm:optimizations,
            llvm:instcombine,
            missed-optimization
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Kmeakin
      </td>
    </tr>
</table>

<pre>
    This is listed in [Synthesizing an instruction selection rule library from semantic specifications](https://dl.acm.org/doi/10.1145/3168821) as an example of patterns that were synthesized by an SMT solver but were missing from both GCC and LLVM.

32-bit example ([godbolt](https://godbolt.org/z/T6PGf9Wed), [alive](https://alive2.llvm.org/ce/z/aCaidJ)):
```c
bool src(int32_t x) { return x < ~x; }

bool tgt(int32_t x) { return x < 0; }
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyFU11v2yAU_TX4BdWywXbsBz-0yVZta6VJrbbHCfBNzIZNBDhL-ut3cdw0mypNwnDx_eCcw0Xa7tQ-99pTHEb7AB3VIyXl3dNpDD14_aLHHRUj_vXBTSpoO1IPBs6WmwxgnnTCnejW2QF9gxiDVtTvQemtViIGelJuCKv7EPae8FvCPuLoTCrUkFq3ixurcc6zNM-LEi2eV3XNcsIaKnwEAEcx7PE0u6V7EQK40dPQi0B_gwPqX-EiAXmK8U-Pz9RbcwBH5bREDdr7yGdGKm3o6f16jcEdfXj49piSbEOy2_PM2Y3U4XIqgkdRdraT1oT3yCyuhc0Lfs_V1_tt8x065EDYOooqjD7Ae9mzg6XGHF71ULCUEWuhu89zjSbGnzFW2Xmo815aa6h3CgvrMXD2I9BjlI6s7qiDMLmRHinhCGL14Uj4Ha6ba7ZzftiF_-Znfye_wkigzauK5QXnBU-6lncNb0QSdDDQIvFP2D1rO0g9Rvp0MSlmXsGqMuyyYN_-zpUnZ9p_pNahn2Sq7ICbKNmy3Oyd_YmNiVu85wk8GuWq5CzpW97wrFJN1XQNlJLlikHRFVCLJudQ1CIxQoLxESthbC7Kb-0-6EG_LB3M2HyLF298EWrhdPHFDoPu5jozOstNoluWMZY1GctrhnO6VWVdiqwAXohciZwUGb4dbS5dkLh2piWnnUdnfJ7-zSmwlXcjzPLG-mIKvXXtlwHELz0mswLtTP8PotYzBg">