<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/57411>57411</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Suboptimal code emitted for AVX2 gather intrinsics
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:X86
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          fzhinkin
      </td>
    </tr>
</table>

<pre>
    LLVM explicitly zero out a destination register for AVX2 gather intrinsics, but it's not required as a mask register is always filled with 1's and the destination register will be overridden by vpgather* instruction anyway.

For example,
```
__m256i gather(const long long* base, __m256i index) {
    return _mm256_i64gather_epi64(base, index, 8);
}
```
will be compiled into
```
vpcmpeqd       ymm2, ymm2, ymm2  ;; set up the mask, all ones
vpxor          xmm1, xmm1, xmm1  ;; redundant op, ymm1 will be overridden below
vpgatherqq     ymm1, ymmword ptr [rdi + 8*ymm0], ymm2
vmovdqa        ymm0, ymm1
ret
```
where `vpxor` is redundant.

For comparison, GCC doesn't  zero out a destination register (at least for intrinsics operating on integer values): https://godbolt.org/z/rcbdo4bKT
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJyFVEuPmzAQ_jVwGTWKTR7kwCHJKj10e2q12ltk8JC4a2ximzz213dMwmbVpqoFmMEz33zzorTyUjw_v3wHPLdaVSroC7yjs2C7AAIk-qCMCMoacLhTPqCD2jpYvrxy2ImwJ1mZ4JTxqvIJX0NJhiokfO7B2EBWh045lCA84TXCv92BFH3SJ3HxUCutSeekwh5YbyuMBEJ_zOBE6lAi2CM6p6REA-UFju2VUMKXxMkH11W9mTAXcjJKxk_JeHl9bigEPIum1Uicbyez8e3qxe224dOZggEzryxhgrZm1z-il1L4aA-DrjISzwlfQDJfXVGAlsPQOQPbJipt1WxyhdxiS-8EPKDcrNeQE0SS3RCS-dNDfkMOKtu0KiaPymAfah7bqmnxIOG6LsQjevm8A0R_2Qo8BujaPvOxVvFckB9r0A9gZ8rdxzo3DYtKn_cPMCp7Z6QwAWx788Qe1g61PQ3w1-QcDgNXdrM8WSehDQ6S6cpJBQlfxUQt6WicTJ8-IrrCNPYoDwLuIY8HAlcFqsnjrJJvBBL7OGmPTfoRx189FJMvnPLWRPiv6zVIi56EeYD_zhGVXlBDoaC2ijN1nyPKFzrSplYjA_qOO9I_Ct1RGWJvLGEfQuvpJeEbunZWllaHkXXUl5t3ul1VSjspv_1MsWCzGZvlCzadpLLI5CJbiDTQqGPxoyttG1QjNIUiEbBRIVAv_XvE087p4g_nNLVdOaJckKD1cdi-tM7-wor-BRvlfU99M51PGEv3xZzVdcYneclZLljJsimfsRyreZ3hFGWVakFd4QsqdsJ5Kao3NJI8vuYzkqneqSr4mPNxznPG2YJNRnNZyypnNZKY1TxLJmNshNKjyCVmJnVFT6vsdp4ONVXB3w-F92pnEHuXhC-6sLeuqN_3yrwpk_YhFD3_3yYZpoA">