<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/57181>57181</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            possible miscompile of signext-of-i1 by aarch64 backend
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          regehr
      </td>
    </tr>
</table>

<pre>
    we think this is getting miscompiled:
```llvm
define i32 @assertsext_sub_1(i1 signext %0, i32 %1) {
  %3 = zext i1 %0 to i32
  %4 = sub i32 %1, %3
  ret i32 %4
}
```

the default aarch64 backend emits:
```
assertsext_sub_1:
        add     w0, w1, w0
        ret
```

or see here: https://gcc.godbolt.org/z/rYPc3cqE8

so now let's work through the example. call the function with `%0 = 1` and `%1 = 0` and I think we can agree the function should return -1, but the ARM code returns 1 for this input. 

this feels perhaps related to the fact that the aarch64 ABI implicitly zero-extends an i1 into an i8

cc @aemerson @ornata @nunoplopes @ryan-berger @nbushehri @zhengyang92
</pre>
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