<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/57166>57166</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            DAGCombine carry folding makes code worse in given testcase
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:ARM,
            llvm:codegen
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          efriedma-quic
      </td>
    </tr>
</table>

<pre>
    Testcase derived from boringssl: [boringssl-bcm-testcase.txt](https://github.com/llvm/llvm-project/files/9339270/boringssl-bcm-testcase.txt).  The code is sort of complicated, but I'm not sure how to simplify it.

I've found that if I revert D64190 (e9aed963ce36) and D57302 (bddb8c359739), the generated code for the given testcase is significantly shorter on both 32-bit x86 and 32-bit ARM.  The effect is a bit more obvious on ARM, where the mrs/msr operations to spill the carry bit are more distinct, but it's significant either way.

I think what's happening is that the we do some combines that seem to improve the code locally, but end up forcing the scheduler to spill the carry bit, which then makes the code worse overall.  Or maybe the scheduler just doesn't realize it should avoid spilling the carry bit?  Not quite sure which.

64-bit targets don't have the same issue on the given testcase, but I assume that's because of the integer widths involved, not because 64-bit targets are somehow immune to the issue.

On a related note, we might want to teach the ARM backend to use a different sequence to save/restore the carry bit, if we expect carry spills to show up in practical code.  msr/mrs appear to be slower than other ways of accessing the carry bit.

CC @topperc @RKSimon @deadalnix 
</pre>
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