<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/57122>57122</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [ARM] Some bitwise logic instructions used by cmp-ne-zero are not combined into S-suffixed versions
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:ARM
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            fzhinkin
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          fzhinkin
      </td>
    </tr>
</table>

<pre>
    Majority of bitwise logic instructions have 'S'-version which update status flags but only subset of these instructions is supported by the `ARMBaseInstrInfo::optimizeCompareInstr` peephole.

For example, ORR with shifted second operand is not supported by the peephole:
https://godbolt.org/z/536GvzfP4
```
bool cmp_ne_orr_rsr(uint32_t a, uint32_t b) {
    return (a | (b << 2)) != 0;
}
```
is currently compiled into:
```
cmp_ne_orr_rsr(unsigned int, unsigned int):
        orr     r0, r0, r1, lsl #2
        cmp     r0, #0
        movwne  r0, #1
        bx      lr
```
but a bit more optimal code will look like:
```
cmp_ne_orr_rsr(unsigned int, unsigned int):
        orrs    r0, r0, r1, lsl #2
        movwne  r0, #1
        bx      lr
```

The same is true for AND, ORR, EOR with shifted register operand and all versions of BIC.

The peephole also ignores shift instructions (except T2's LSR and LSL).
</pre>
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