<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/57010>57010</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            GlobalISel should be able to generically select debug instructions 
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            globalisel
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            aemerson,
            arsenm,
            ornata
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          arsenm
      </td>
    </tr>
</table>

<pre>
    Debug pseudoinstructions require selection support in order to ensure the operands are always constrained to a register class after selection. https://reviews.llvm.org/D129037 is a partial fix which duplicates code in AArch64 and X86 in order to handle this. We should treat these generically, similar to how G_ASSERT_* optimization hints are handled. We need some sort of API in RBI/TRI to allow generic code to constrain operands of simple instructions given a TargetRegisterClass and LLT
</pre>
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