<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/56911>56911</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
LLVM 15 regression: fpext half to fp128
</td>
</tr>
<tr>
<th>Labels</th>
<td>
bug,
backend:X86,
regression
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
andrewrk
</td>
</tr>
</table>
<pre>
release/15.x branch, commit 0214d986fb64f89cc75289199100475af2e73870
Based on the following downstream test case:
```zig
test "cast f16 to f128" {
var x: f16 = 1234.0;
try expect(@as(f128, 1234.0) == x);
}
```
LLVM IR reduction. Expected `main` to return 0, however it returns 1.
```llvm
source_filename = "test"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define i8 @main() unnamed_addr #1 {
Entry:
%result = alloca i8, align 1
%x = alloca half, align 2
store half 0xH64D2, ptr %x, align 2
%0 = load half, ptr %x, align 2
%1 = fpext half %0 to fp128
%2 = call i32 @__eqtf2(fp128 0xL00000000000000004009348000000000, fp128 %1)
%3 = icmp eq i32 %2, 0
br i1 %3, label %Then, label %Else
Then: ; preds = %Entry
store i8 0, ptr %result, align 1
%4 = load i8, ptr %result, align 1
ret i8 %4
Else: ; preds = %Entry
store i8 1, ptr %result, align 1
%5 = load i8, ptr %result, align 1
ret i8 %5
}
define i32 @__eqtf2(fp128 %0, fp128 %1) #1 {
Entry:
%result = alloca i32, align 4
%a = alloca fp128, align 16
%b = alloca fp128, align 16
store fp128 %0, ptr %a, align 16
store fp128 %1, ptr %b, align 16
%2 = load fp128, ptr %a, align 16
%3 = load fp128, ptr %b, align 16
%4 = call i32 @__cmptf2(fp128 %2, fp128 %3)
store i32 %4, ptr %result, align 4
%5 = load i32, ptr %result, align 4
ret i32 %5
}
define i32 @__cmptf2(fp128 %0, fp128 %1) #1 {
Entry:
%result = alloca i32, align 4
%2 = alloca fp128, align 16
%3 = alloca fp128, align 16
%a = alloca fp128, align 16
%b = alloca fp128, align 16
store fp128 %0, ptr %a, align 16
store fp128 %1, ptr %b, align 16
%4 = load fp128, ptr %a, align 16
store fp128 %4, ptr %2, align 16
%5 = load fp128, ptr %b, align 16
store fp128 %5, ptr %3, align 16
%6 = call fastcc i32 @compiler_rt.comparef.cmpf2.73(fp128 %4, fp128 %5)
store i32 %6, ptr %result, align 4
%7 = load i32, ptr %result, align 4
ret i32 %7
}
define internal fastcc i32 @compiler_rt.comparef.cmpf2.73(fp128 %0, fp128 %1) unnamed_addr #3 {
Entry:
%result = alloca i32, align 4
%aInt = alloca i128, align 16
%bInt = alloca i128, align 16
%aAbs = alloca i128, align 16
%bAbs = alloca i128, align 16
%a = alloca fp128, align 16
%b = alloca fp128, align 16
store fp128 %0, ptr %a, align 16
store fp128 %1, ptr %b, align 16
%2 = load fp128, ptr %a, align 16
store fp128 %2, ptr %aInt, align 16
%3 = load fp128, ptr %b, align 16
store fp128 %3, ptr %bInt, align 16
%4 = load i128, ptr %aInt, align 16
%5 = and i128 %4, 170141183460469231731687303715884105727
store i128 %5, ptr %aAbs, align 16
%6 = load i128, ptr %bInt, align 16
%7 = and i128 %6, 170141183460469231731687303715884105727
store i128 %7, ptr %bAbs, align 16
%8 = load i128, ptr %aAbs, align 16
%9 = icmp ugt i128 %8, 170135991163610696904058773219554885632
br i1 %9, label %BoolOrTrue, label %BoolOrFalse
BoolOrFalse: ; preds = %Entry
%10 = load i128, ptr %bAbs, align 16
%11 = icmp ugt i128 %10, 170135991163610696904058773219554885632
br label %BoolOrTrue
BoolOrTrue: ; preds = %BoolOrFalse, %Entry
%12 = phi i1 [ %9, %Entry ], [ %11, %BoolOrFalse ]
br i1 %12, label %Then, label %Else
Then: ; preds = %BoolOrTrue
store i32 1, ptr %result, align 4
%13 = load i32, ptr %result, align 4
ret i32 %13
Else: ; preds = %BoolOrTrue
br label %EndIf
EndIf: ; preds = %Else
%14 = load i128, ptr %aAbs, align 16
%15 = load i128, ptr %bAbs, align 16
%16 = or i128 %14, %15
%17 = icmp eq i128 %16, 0
br i1 %17, label %Then1, label %Else2
Then1: ; preds = %EndIf
store i32 0, ptr %result, align 4
%18 = load i32, ptr %result, align 4
ret i32 %18
Else2: ; preds = %EndIf
br label %EndIf3
EndIf3: ; preds = %Else2
%19 = load i128, ptr %aInt, align 16
%20 = load i128, ptr %bInt, align 16
%21 = and i128 %19, %20
%22 = icmp sge i128 %21, 0
br i1 %22, label %Then4, label %Else9
Then4: ; preds = %EndIf3
%23 = load i128, ptr %aInt, align 16
%24 = load i128, ptr %bInt, align 16
%25 = icmp slt i128 %23, %24
br i1 %25, label %Then5, label %Else6
Then5: ; preds = %Then4
store i32 -1, ptr %result, align 4
%26 = load i32, ptr %result, align 4
ret i32 %26
Else6: ; preds = %Then4
%27 = load i128, ptr %aInt, align 16
%28 = load i128, ptr %bInt, align 16
%29 = icmp eq i128 %27, %28
br i1 %29, label %Then7, label %Else8
Then7: ; preds = %Else6
store i32 0, ptr %result, align 4
%30 = load i32, ptr %result, align 4
ret i32 %30
Else8: ; preds = %Else6
store i32 1, ptr %result, align 4
%31 = load i32, ptr %result, align 4
ret i32 %31
Else9: ; preds = %EndIf3
%32 = load i128, ptr %aInt, align 16
%33 = load i128, ptr %bInt, align 16
%34 = icmp sgt i128 %32, %33
br i1 %34, label %Then10, label %Else11
Then10: ; preds = %Else9
store i32 -1, ptr %result, align 4
%35 = load i32, ptr %result, align 4
ret i32 %35
Else11: ; preds = %Else9
%36 = load i128, ptr %aInt, align 16
%37 = load i128, ptr %bInt, align 16
%38 = icmp eq i128 %36, %37
br i1 %38, label %Then12, label %Else13
Then12: ; preds = %Else11
store i32 0, ptr %result, align 4
%39 = load i32, ptr %result, align 4
ret i32 %39
Else13: ; preds = %Else11
store i32 1, ptr %result, align 4
%40 = load i32, ptr %result, align 4
ret i32 %40
}
attributes #1 = { nobuiltin nounwind "frame-pointer"="all" "probe-stack"="__zig_probe_stack" "target-cpu"="skylake" "target-features"="-16bit-mode,-32bit-mode,-3dnow,-3dnowa,+64bit,+adx,+aes,-amx-bf16,-amx-int8,-amx-tile,+avx,+avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxvnni,+bmi,+bmi2,-branchfusion,-cldemote,+clflushopt,-clwb,-clzero,+cmov,+crc32,+cx16,+cx8,-enqcmd,+ermsb,+f16c,-false-deps-getmant,-false-deps-lzcnt-tzcnt,-false-deps-mulc,-false-deps-mullq,-false-deps-perm,+false-deps-popcnt,-false-deps-range,-fast-11bytenop,+fast-15bytenop,-fast-7bytenop,-fast-bextr,+fast-gather,-fast-hops,-fast-lzcnt,-fast-movbe,+fast-scalar-fsqrt,-fast-scalar-shift-masks,+fast-shld-rotate,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle,+fast-vector-fsqrt,-fast-vector-shift-masks,+fma,-fma4,+fsgsbase,-fsrm,+fxsr,-gfni,-harden-sls-ijmp,-harden-sls-ret,-hreset,-idivl-to-divb,+idivq-to-divl,+invpcid,-kl,-lea-sp,-lea-uses-ag,-lvi-cfi,-lvi-load-hardening,-lwp,+lzcnt,+macrofusion,+mmx,+movbe,-movdir64b,-movdiri,-mwaitx,+nopl,-pad-short-functions,+pclmul,-pconfig,-pku,+popcnt,-prefer-128-bit,-prefer-256-bit,-prefer-mask-registers,-prefetchwt1,+prfchw,-ptwrite,-rdpid,-rdpru,+rdrnd,+rdseed,-retpoline,-retpoline-external-thunk,-retpoline-indirect-branches,-retpoline-indirect-calls,-rtm,+sahf,-sbb-dep-breaking,-serialize,-seses,+sgx,-sha,-shstk,+slow-3ops-lea,-slow-incdec,-slow-lea,-slow-pmaddwd,-slow-pmulld,-slow-shld,-slow-two-mem-ops,-slow-unaligned-mem-16,-slow-unaligned-mem-32,-soft-float,+sse,+sse2,+sse3,+sse4.1,+sse4.2,-sse4a,-sse-unaligned-mem,+ssse3,-tagged-globals,-tbm,-tsxldtrk,-uintr,-use-glm-div-sqrt-costs,-use-slm-arith-costs,-vaes,-vpclmulqdq,+vzeroupper,-waitpkg,-wbnoinvd,-widekl,+x87,-xop,+xsave,+xsavec,+xsaveopt,+xsaves" }
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzVWktv4zgS_jXORVAgknoecuhMd2MHmMUCu4PF3gJKomxNqEdIynb3r98iqZcl2-vEGSwmCOxischiVX1VJGWlTf7jSTDOqGQb_B0Fj0cnFbTOdhv8i5M1VVUqx8PIz5M4LNLQL-Iky6IAxwlKEuR5fhTQArOIxJG38b5uvC_28xkmzJ2mdtSOOUXDeXMo662TN4daKsFo5SgmlZNpveTLfOQm9Oz_z3JrOUZygzEIK6dAoaMa-MIxsJxN9GyFHPjbU-EcYTojtCFfHYSJ_-htyExGiR8OO7YsUxuYwfeohG872y-DPE70aD3BEehx-Cb6uljifN2__fbvvzu__tMRLO8yVTb1o_PN6AE_gGhFyxq-9NoFU52oHU9r3DUHtmfCATdbtnTQ41l3cL6vLEs2ncjYS1FyVtOKGUvBF9pN8NX7jIotU05OFeX0R9OpQYq5FXiIuS2GgJEvBJsP3USnTU2Fvvlwy4EoYj0IvOXWsSbCYQz0_cuG5ES_EmXLxxUe4_AFBLv6tQYcuLysu6O7rbtxlP3MWVHWzCljB-Jj_KYnTpyu1ubmLzTPBUxH0BT9bzXEdQSSA72BYLLj1mwK8MsoTKg9Tnm5rR00kzzOhXaUF5MYHsSkagQznY53_Fvof8VaqFXCTHBmALA9My9vaD7Oen0AMgOKlh2VVWUm0WhvtW8nQWwEM1iyUxKs3fTywt5UgTWWtSws8jdv8ed7XkL8eGzrNVhhrVoDfVJAjIIyq1qHvVkdoFWP8AapFECLjKxmc5oyrlu_71h9wvjGIcVn0TUCxOTizX-Qgk4LiSV7JAU23iexAbh4Mxfb8J8PuD8FxmLif42B1DRwhKFzU4xpf44p6EZTgo-bEiyr2pkUPA8uDcsVej6UkQRPS_RnonQuZdE_mRLOBNObBK1bTxffO4reID8PRnphIXgKxLiMayrGJDs75JIW_0ziQ5IugoNPgkNmqd3jy-azfwUv_gWMEXzLIAMyq-Q8ypb4WtvwJwMM3wowcqvgXw-y_jshu1Axhw--oCJ4J8QXKoKZPLmgIpxSooADYpYNqILTawtHJPEi1KOmqWDFIwCtwI8RmUPNP4FacCldwhvTJbonXaKr6VIrJmr6YUPP5NTyTEU-rYL_Wp8KXkmI20Xpl1TeOuvton-91H3vbrNQMUelDtQnbVALLWQuf1nL_DS2MOXyIFtYaG3HjFmMIg_5CMXEDz0_TGDDiAgK44h4JEJBHPvICyIcLfL7TLXRQLtacM6t94qR0Wq94d3rjeaqL683vuzfy4OS6QLQbdWoMh4WTQK4_qOQhMgLkzCBy0UQRxHBKAkCP46DkIwXm_GikJzcC56bhv9D_C46dob9nS5uDXP2rSfu60dtnWne5VBedg1C532DvI8555xHVpYb7s1XjZXlc_fBIs_5wpaUdleaaAXPY8QGYWB-NW3bh1DfOZvbiCzDjvD_4YK49OV8L792t5pvYYjcs5Mj8ulXxbVRc_h8q_NfixOdhvE-peucGaNjfXKlWl9JmeBDiWYrbSOmFPN7zKFgLhedPq0YhMPzzytQtMIjWgESLxGJ7nbkFJ45GK89szgBY3wXGOMlGPGn2rPCIVkBkbxP4VkgnjwsSz5ybsBXSv6VUWi1faOhNmJvLognKMrttFVjdB6LeF0b_RUWkyUW_U-JHZmvm3zImZeLwTVnBjMf8Wn_xGTwqL_2U7DyU7DyU7j0U3Cvn6yzVznr3rqD4PCepMXhMmnDTzVIq4g-FPfLR8prcU_OlmkcDWGP12FPVmGPVmGPl2GPPmPPCz9eqol3T9SJt4x6_CfZcyuKCbrLHrS0J_n08kXwR2BMLhe9KzAm_rzET-XLOsZMu8Ix8Vc4treFEyAjtEQy8j5h0zzzNOvmAkbuevZLgmXo0TuPUdcN0iou38avRf5y2bsW-fhsASPhEPhoHfh4HXi8DjxZBf6dx7OzfkLojhqW3BX4ZBX4zzj-nTPoViT7dxVlfyjKp89lqVKiTDvFYJm4L5Ob6Nmpm7QruSproLr6UMK5cYNxIWjF3LYxj3H1b94E7tOYcm5eZMC4FU3KXKlo9jr2vrz8LLcvpudl6NGy9vd1N2u7UVS-_uD0lZ0KFIyqDiwcpVwUpqVyqybXTwJcgk9aed0cRkI_Sdzg59AHEUvS_NgTesZfXFod3bQwFy1Dg2XxQKuSs154fxwJbLr3xwDhcaBtlYry7ax9mOgsn-j8baK1Fwe6mJHtfOKyqOjUamdy-7QqT1uz1e35jK7ruWCLTQSleYdk4jZtVqtxef0YsNpqsYRRYF-wKTpZNvpJiJvxnFWN6r2V8YJ3cte0yvYdUvv9k4mml6iafU-JzEBZk0djtKFMDFj9llW5ZTFRydSS4PRMdxf6eY2bs1a6gJOKmqo35_KfYI6r9Oeip-r4cgpg8bcFrwWtvc4Z03hpIQn-2DLLk8pFKP2hWN20w2DNCyaelYqWjJQdlZgN2VK1swAxTXCoHBt8skpq9O9TNhspM8qpcAv5Jiahnil3ZQEjqHyV8xE7nruiUVTN59lTUdKUMzcTjZSc1pDcu64o-FkhcNclEQBas1xPz1yvx6IdvvyeIbcyNa93AVeOITlK45ttYaG9oyJntSu5dMs_qnbBgkpoOFBILFXm5Z67qnHhuweWZr31LN6z6n2blSZ5X006cUZd2Q5UJ5l0qcl5vi_drCgHUlfpXn9ZW4FDD4chdEBWFBw7ppFmVH2hGSKqQ5uXAirY1DBKqgMtVS8MIDKLa0En5J2AotnV5g2u3qVtxgHfRiRr6qI0C2pfu753RDTsVwUTrn47ylbMgYODcMHRAQOvbkupC8nYobLdQaF-XlFAy3SpgygNslyRt9afQIh-ASIXdT6QkjHbz1Tb8LJmJw0XcsT8guiqXVe_nvbBLlUKQFVfn2yFP9Otf2q1faoHk6Q7U1ZlmuqEhgkYfe0DJxngm5c_mW1I1jtVbo-Gs6P2S6rXvoM3B5c0ugIx26cZZZ3lLBub8662onl-yGdtKEZTU-fm2FCHxq1Y5fbFwPC62uz7LDc9dus402EKrSsbSLcC8NljUEo2EnikyEj5j2hG2ymAoj1xqmOQtBO4im630LHlTUqtx1VamS955LkSJn4d7EUmkyGbQLTS6efqSuFmjVRy6JHQA5VG7Sb2vt_E9xbfb2brAv17vdN0bWuLp06U9tWE8pDWcHbZG28eypy99ml-jPWl3D0OFfso6Z7NyGxG221taEn7CudwphpedXxgTygMkiAKEoQe8ieSJyShD6pUnD2Z9yxRAKezLZQjk_z6jc_ppbnhfbmHTvCnnVIQavJlg7_D_xYc0KX6R3JomBcq7RdkX_OH2c6_l1J2el3fg1Ar3z1lPkuY52U4iZOgCDwUsiSKQ0QiSqMw9B_MUV4-bYJnsCbtthvc3wRxCuc1BrlJvvwnDif2bOXAC74-lE_Yw9iLPd_TvwV6j1GWhUlBg9wjiUfhqut7rKIlf9SLfWzE9kE8mXWDOgmdHOqInDopTA6YYmZNMD_tFNS1J1rngh3E64Ox8ckY-F-d49yG">